Kai Huang

IEICE Electron. Express, 2024

Structural analysis attack on asynchronous obfuscated circuits.

[BibT_eX]

[DOI]

Zihe Wang

Dongliang Xiong

IEICE Electron. Express, 2024

FCLock: harnessing functional non-combinational cycles in logic locking.

[BibT_eX]

[DOI]

Xiang Chen

Dandan Zheng

IEICE Electron. Express, 2024

2023

Structured Dynamic Precision for Deep Neural Networks Quantization.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., January, 2023

Efficient Halftoning via Deep Reinforcement Learning.

[BibT_eX]

[DOI]

IEEE Trans. Image Process., 2023

Structured Term Pruning for Computational Efficient Neural Networks Inference.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Fast halftoning policy network with error feedback.

[BibT_eX]

[DOI]

J. Electronic Imaging, 2023

SILL: Preventing structural attack for logic locking.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2023

A 1.8V 16μA 136.5dB DR PPG/NIRS Recording IC using Noise Shaping Triple Slope Light to Digital Converter.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

Acceleration-Aware Fine-Grained Channel Pruning for Deep Neural Networks via Residual Gating.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Flexible and Dynamic Scheduling of Mixed-Criticality Systems.

[BibT_eX]

[DOI]

Sensors, 2022

Structured precision skipping: Accelerating convolutional neural networks with budget-aware dynamic precision selection.

[BibT_eX]

[DOI]

J. Syst. Archit., 2022

Sample-wise dynamic precision quantization for neural network acceleration.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2022

Halftoning with Multi-Agent Deep Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Image Processing, 2022

2021

Expected Energy Optimization for Real-Time Multiprocessor SoCs Running Periodic Tasks with Uncertain Execution Time.

[BibT_eX]

[DOI]

IEEE Trans. Sustain. Comput., 2021

DPOQ: Dynamic Precision Onion Quantization.

[BibT_eX]

[DOI]

Proceedings of the Asian Conference on Machine Learning, 2021

2020

Trigger Identification Using Difference-Amplified Controllability and Dynamic Transition Probability for Hardware Trojan Detection.

[BibT_eX]

[DOI]

Yun He

IEEE Trans. Inf. Forensics Secur., 2020

Fine-Grained Channel Pruning for Deep Residual Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2020, 2020

IdleSR: Efficient Super-Resolution Network with Multi-scale IdleBlocks.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2020 Workshops, 2020

Adaptive Hybrid Composition Based Super-Resolution Network via Fine-Grained Channel Pruning.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2020 Workshops, 2020

DFQF: Data Free Quantization-aware Fine-tuning.

[BibT_eX]

[DOI]

Proceedings of The 12th Asian Conference on Machine Learning, 2020

2019

A Real-Time High-Quality Complete System for Depth Image-Based Rendering on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2019

A Scalable and Adaptable ILP-Based Approach for Task Mapping on MPSoC Considering Load Balance and Communication Optimization.

[BibT_eX]

[DOI]

Ahmed Amine Jerraya

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Holistic hardware Trojan design of trigger and payload at gate level with rare switching signals eliminated.

[BibT_eX]

[DOI]

Yun He

Xiaowen Jiang

IEICE Electron. Express, 2019

Fine-Grained Communication-Aware Task Scheduling Approach for Acyclic and Cyclic Applications on MPSoCs.

[BibT_eX]

[DOI]

IEEE Access, 2019

NoUCSR: Efficient Super-Resolution Network without Upsampling Convolution.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision Workshops, 2019

2018

Curve fitting based shared cache partitioning scheme for energy saving.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

BFCO: A BPSO-Based Fine-Grained Communication Optimization Method for MPSoC.

[BibT_eX]

[DOI]

IEEE Access, 2018

Energy-Efficient Fault-Tolerant Mapping and Scheduling on Heterogeneous Multiprocessor Real-Time Systems.

[BibT_eX]

[DOI]

IEEE Access, 2018

The Recognition of Driving Action Based on EEG Signals Using Wavelet-CSP Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Detection of movement-related cortical potentials associated with emergency and non-emergency tasks.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

2017

Providing Predictable Performance via a Slowdown Estimation Model.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2017

A Hybrid Multi-objective Evolutionary Algorithm for Energy-Aware Allocation and Scheduling Optimization of MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Tools with Artificial Intelligence, 2017

User Perceived Value-Aware Cloud Pricing for Profit Maximization of Multiserver Systems.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Parallel and Distributed Systems, 2017

High-quality view interpolation based on depth maps and its hardware implementation.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

Memory Access Scheduling Based on Dynamic Multilevel Priority in Shared DRAM Systems.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2016

Improving the efficiency of functional verification based on test prioritization.

[BibT_eX]

[DOI]

Shupeng Wang

Microprocess. Microsystems, 2016

Reconfigurable cache for real-time MPSoCs: Scheduling and implementation.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture Design in FPGA.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

SoC oriented real-time high-quality stereo vision system.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

SoC and FPGA oriented high-quality stereo vision system.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

Functional Testbench Qualification by Mutation Analysis.

[BibT_eX]

[DOI]

VLSI Design, 2015

Communication Optimizations for Multithreaded Code Generation from Simulink Models.

[BibT_eX]

[DOI]

Ahmed Amine Jerraya

Jiong Feng

ACM Trans. Embed. Comput. Syst., 2015

Profiling and annotation combined method for multimedia application specific MPSoC performance estimation.

[BibT_eX]

[DOI]

Frontiers Inf. Technol. Electron. Eng., 2015

Hybrid Model: An Efficient Symmetric Multiprocessor Reference Model.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2015

2014

Communication-oriented performance optimisation during code generation from Simulink models.

[BibT_eX]

[DOI]

Int. J. Embed. Syst., 2014

ILP Based Multithreaded Code Generation for Simulink Model.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

Automatic cache partitioning and time-triggered scheduling for real-time MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Annotation and analysis combined cache modeling for native simulation.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Performance Estimation Techniques With MPSoC Transaction-Accurate Models.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding.

[BibT_eX]

[DOI]

J. Zhejiang Univ. Sci. C, 2013

Communication Pipelining for Code Generation from Simulink Models.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Trust, 2013

2010

A high efficient memory architecture for H.264/AVC motion compensation.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009

Simulink<sup>®</sup>-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation.

[BibT_eX]

[DOI]

Sang-Il Han

Soo-Ik Chae

Integr., 2009

2007

Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264.

[BibT_eX]

[DOI]

Sang-Il Han

Katalin Popovici