Kai-Chiang Wu

Orcid: 0009-0000-6931-6538

According to our database¹, Kai-Chiang Wu authored at least 57 papers between 2004 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

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In proceedings

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PhD thesis

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Links

On csauthors.net:

Bibliography

2024

Reliability Engineering in a Time of Rapidly Converging Technologies.

[BibT_eX]

[DOI]

Shiuhpyng Winston Shieh

IEEE Trans. Reliab., March, 2024

ELSA: Exploiting Layer-wise N:M Sparsity for Vision Transformer Acceleration.

[BibT_eX]

[DOI]

CoRR, 2024

Palu: Compressing KV-Cache with Low-Rank Projection.

[BibT_eX]

[DOI]

CoRR, 2024

FLORA: Fine-grained Low-Rank Architecture Search for Vision Transformer.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024

Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods.

[BibT_eX]

[DOI]

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Synergizing GCN and GAT for Hardware Trojan Detection and Localization.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2024

ELSA: Exploiting Layer-wise N: M Sparsity for Vision Transformer Acceleration.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2024

2023

CNN-Based Stochastic Regression for IDDQ Outlier Identification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Test Generation for Defect-Based Faults of Scan Flip-Flops.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Outlier Detection for Analog Tests Using Deep Learning Techniques.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2023

Using Path Features for Hardware Trojan Detection Based on Machine Learning Techniques.

[BibT_eX]

[DOI]

Chia-Heng Yen

Jung-Che Tsai

Kai-Chiang Wu

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Decomposable Architecture and Fault Mitigation Methodology for Deep Learning Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Q-YOLOP: Quantization-Aware You Only Look Once for Panoptic Driving Perception.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Multimedia and Expo Workshops, 2023

MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2023

2022

Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs.

[BibT_eX]

[DOI]

Ning-Chi Huang

Chao-Wei Cheng

Kai-Chiang Wu

IEEE Trans. Very Large Scale Integr. Syst., 2022

Test Methodology for Defect-Based Bridge Faults.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Methodology of Generating Timing-Slack-Based Cell-Aware Tests.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Rule Generation for Classifying SLT Failed Parts.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Improving Cell-Aware Test for Intra-Cell Short Defects.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Highly Uniform All-Vacuum-Deposited Inorganic Perovskite Artificial Synapses for Reservoir Computing.

[BibT_eX]

[DOI]

Adv. Intell. Syst., 2021

Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

An Energy-Efficient Approximate Systolic Array Based on Timing Error Prediction and Prevention.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

FOX-NAS: Fast, On-device and Explainable Neural Architecture Search.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF International Conference on Computer Vision Workshops, 2021

The 2020 Low-Power Computer Vision Challenge.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

Making Aging Useful by Recycling Aging-induced Clock Skew.

[BibT_eX]

[DOI]

Tien-Hung Tseng

Chung-Han Chou

Kai-Chiang Wu

ACM Trans. Design Autom. Electr. Syst., 2020

CNN-based Stochastic Regression for IDDQ Outlier Identification.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator.

[BibT_eX]

[DOI]

Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

Test Methodology for Defect-based Bridge Faults.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2020

Selective Sensor Placement for Cost-Effective Online Aging Monitoring and Resilience.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

2019

Layout-Based Dual-Cell-Aware Tests.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs.

[BibT_eX]

[DOI]

Ning-Chi Huang

Yu-Guang Chen

Kai-Chiang Wu

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

ICE-RADAR: In-situ, Cost-Effective Razor Flip-Flop Deployment for Aging Resilience.

[BibT_eX]

[DOI]

Kai-Chiang Wu

Wei-Tao Huang

Chiao-Yang Huang

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications.

[BibT_eX]

[DOI]

Ning-Chi Huang

Szu-Ying Chen

Kai-Chiang Wu

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Aging-aware chip health prediction adopting an innovative monitoring strategy.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Sensor-Based Time Speculation in the Presence of Timing Variability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

MAUI: Making aging useful, intentionally.

[BibT_eX]

[DOI]

Kai-Chiang Wu

Tien-Hung Tseng

Shou-Chun Li

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Lifetime Reliability Trojan Based on Exploring Malicious Aging.

[BibT_eX]

[DOI]

Tien-Hung Tseng

Shou-Chun Li

Kai-Chiang Wu

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Fast WAT test structure for measuring Vt variance based on latch-based comparators.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Workload-aware lifetime Trojan based on statistical aging manipulation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017

Analysis and optimization of variable-latency designs in the presence of timing variability.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2014

Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment.

[BibT_eX]

[DOI]

Kai-Chiang Wu

Diana Marculescu

IEEE Trans. Very Large Scale Integr. Syst., 2014

NBTI and Leakage Reduction Using ILP-Based Approach.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013

A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits.

[BibT_eX]

[DOI]

Kai-Chiang Wu

Diana Marculescu

IEEE Trans. Very Large Scale Integr. Syst., 2013

2012

Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Aging-aware timing analysis and optimization considering path sensitization.

[BibT_eX]

[DOI]

Kai-Chiang Wu

Diana Marculescu

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Clock skew scheduling for soft-error-tolerant sequential circuits.

[BibT_eX]

[DOI]

Kai-Chiang Wu

Diana Marculescu

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Joint logic restructuring and pin reordering against NBTI-induced performance degradation.

[BibT_eX]

[DOI]

Kai-Chiang Wu

Diana Marculescu

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Power-aware soft error hardening via selective voltage scaling.

[BibT_eX]

[DOI]

Kai-Chiang Wu

Diana Marculescu

Proceedings of the 26th International Conference on Computer Design, 2008

Process variability-aware transient fault modeling and analysis.

[BibT_eX]

[DOI]

Natasa Miskov-Zivanov

Kai-Chiang Wu

Diana Marculescu

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Soft error rate reduction using redundancy addition and removal.

[BibT_eX]

[DOI]

Kai-Chiang Wu

Diana Marculescu

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Contouring Control of Smooth Paths for Multiaxis Motion Systems Based on Equivalent Errors.

[BibT_eX]

[DOI]

Shyh-Leh Chen

Kai-Chiang Wu

IEEE Trans. Control. Syst. Technol., 2007

2006

Delay variation tolerance for domino circuits.

[BibT_eX]

[DOI]

Kai-Chiang Wu

Cheng-Tao Hsieh

Shih-Chieh Chang

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2004

Re-synthesis for delay variation tolerance.

[BibT_eX]

[DOI]

Shih-Chieh Chang

Cheng-Tao Hsieh

Kai-Chiang Wu

Proceedings of the 41th Design Automation Conference, 2004

Kai-Chiang Wu

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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