K. Yamaguchi
According to our database1,
K. Yamaguchi
authored at least 2 papers
between 2017 and 2024.
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Bibliography
2024
Up to 57% Reduction in Effective Resistivity of Word Lines of 3D-NAND Memory by Grain-Size Control, Material Selection, and Seam Removal.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2017
Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017