K. T. Lau

According to our database, K. T. Lau authored at least 10 papers between 1993 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2008

Low Power Adiabatic Programmable Logic Array with Single Clock Iapdl.

W. J. Yang, Y. Zhou, K. T. Lau

J. Circuits Syst. Comput., 2008

Improved Dynamic Current Mode Logic for Low Power Applications.

S. Ramakrishnan, K. T. Lau

J. Circuits Syst. Comput., 2008

2007

Creative design of assistive products for the elderly.

K. T. Lau, Ian Gibson, C. Y. Chow

Proceedings of the 1st international convention on Rehabilitation engineering & assistive technology, 2007

2002

Low Power 16 x 16 Bit Multiplier Design Using PAL-2N Logic Family.

H. H. Wong, K. T. Lau

J. Circuits Syst. Comput., 2002

2000

A Novel Adiabatic Register File Design.

K. W. Ng, K. T. Lau

J. Circuits Syst. Comput., 2000

1999

An Adiabatic 4: 2 Compressor Design for Low Power VLSI.

K. W. Ng, K. T. Lau

J. Circuits Syst. Comput., 1999

1998

Programmable digital neuron using pulsewidth-coded data.

K. T. Lau, S. H. Kang, M. C. Tan, Y. K. Choo

Microprocess. Microsystems, 1998

1995

Design and implementation of an FPGA transponder.

B. H. Tan, E. Tan, K. T. Lau, S. C. Mar

Microprocess. Microsystems, 1995

A reconfigurable low-voltage low-power building block for artificial neural networks.

S. T. Lee, K. T. Lau

Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

1993

Simplified architecture of a fuzzy inference processor.

J. S. Ho, M. H. Lim, K. T. Lau

Proceedings of the First New Zealand International Two-Stream Conference on Artificial Neural Networks and Expert Systems, 1993