K. Sridharan
Orcid: 0000-0001-5279-7830Affiliations:
- Indian Institute of Technology Madras, Chennai, India
- Indian Institute of Technology Guwahati, India (1996 - 2001)
- Rensselaer Polytechnic Institute, Troy, NY USA (PhD 1995)
According to our database1,
K. Sridharan
authored at least 54 papers
between 1992 and 2024.
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Bibliography
2024
Design and Implementation of a Magnetic Coupling Based Segmented Bend Angle Sensor for a Soft Robotic Gripper.
IEEE Trans. Instrum. Meas., 2024
2022
Proceedings of the IEEE Sensors Applications Symposium, 2022
2021
A High-Performance VLSI Architecture for a Self-Feedback Convolutional Neural Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
2020
Protecting an Autonomous Delivery Agent Against a Vision-Guided Adversary: Algorithms and Experimental Results.
IEEE Trans. Ind. Informatics, 2020
A Resource-Efficient Multiplierless Systolic Array Architecture for Convolutions in Deep Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Interval Analysis Technique for Versatile and Parallel Multi-Agent Collision Detection and Avoidance.
J. Intell. Robotic Syst., 2020
2019
Multiagent Gathering With Collision Avoidance and a Minimax Distance Criterion - Efficient Algorithms and Hardware Realization.
IEEE Trans. Ind. Informatics, 2019
Analysing interactions between a trio of differential drive robots via a differential game formulation.
Proceedings of the 2019 American Control Conference, 2019
2018
IET Circuits Devices Syst., 2018
Time Optimal Rendezvous for Multi-Agent Systems Amidst Obstacles - Theory and Experiments.
Proceedings of the IECON 2018, 2018
Hardware-Efficient Velocity Estimation of Dynamic Obstacles Based on a Novel Radix-4 CORDIC and FPGA Implementation.
Proceedings of the IECON 2018, 2018
2017
A Transistor-Level Probabilistic Approach for Reliability Analysis of Arithmetic Circuits With Applications to Emerging Technologies.
IEEE Trans. Reliab., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity.
IEEE Trans. Computers, 2017
IET Circuits Devices Syst., 2017
2016
IEEE Trans. Ind. Electron., 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
2015
Studies in Computational Intelligence 599, Springer, ISBN: 978-3-319-16688-9, 2015
A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular Automata.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Very large-scale integration architecture for video stabilisation and implementation on a field programmable gate array-based autonomous vehicle.
IET Comput. Vis., 2015
2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
2012
New Decomposition Theorems on Majority Logic for Low-Delay Adder Designs in Quantum Dot Cellular Automata.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Efficient VLSI Architectures for the Hadamard Transform Based on Offset-Binary Coding and ROM Decomposition.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
2010
Robotic mapping with simple sensing and processing hardware - Algorithm and architecture.
Proceedings of the 11th International Conference on Control, 2010
2009
IEEE Trans. Ind. Electron., 2009
Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
2008
Robotic Exploration and Landmark Determination: Hardware-Efficient Algorithms and FPGA Implementations.
Studies in Computational Intelligence 81, Springer, ISBN: 978-3-540-75393-3, 2008
Hardware-Efficient Prediction-Correction-Based Generalized-Voronoi-Diagram Construction and FPGA Implementation.
IEEE Trans. Ind. Electron., 2008
2007
VLSI-Efficient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment.
IEEE Trans. Very Large Scale Integr. Syst., 2007
A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations.
IEEE Trans. Ind. Electron., 2007
2006
A parallel algorithm, architecture and FPGA realization for landmark determination and map construction in a planar unknown environment.
Parallel Comput., 2006
A parallel algorithm, architecture and FPGA realization for high speed determination of the complete visibility graph for convex objects.
Microprocess. Microsystems, 2006
A hardware-efficient scheme and FPGA realization for computation of single pair shortest path for a mobile automaton.
Microprocess. Microsystems, 2006
2005
The Design of a Hardware Accelerator for Real-Time Complete Visibility Graph Construction and Efficient FPGA Implementation.
IEEE Trans. Ind. Electron., 2005
Robotics Auton. Syst., 2005
2004
A high-speed VLSI design and ASIC implementation for constructing Euclidean distance-based discrete Voronoi diagram.
IEEE Trans. Robotics Autom., 2004
Hardware-efficient schemes for logarithmic approximation and binary search with application to visibility graph construction.
IEEE Trans. Ind. Electron., 2004
A parallel algorithm for constructing reduced visibility graph and its FPGA implementation.
J. Syst. Archit., 2004
An Efficient Algorithm to Construct Reduced Visibility Graph and Its FPGA Implementation.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
2002
IEEE Trans. Instrum. Meas., 2002
Efficient computation of a measure of depth between convex objects for graphics applications.
Comput. Graph., 2002
2001
Computation of a penetration measure between 3D convex polyhedral objects for collision detection.
J. Field Robotics, 2001
2000
Comput. Appl. Eng. Educ., 2000
1999
Fuzzy Sets Syst., 1999
Proceedings of the 1999 IEEE International Conference on Robotics and Automation, 1999
1998
Computation of penetration measures for convex polygons and polyhedra for graphics applications.
Proceedings of the 5th International Conference On High Performance Computing, 1998
1994
Inf. Process. Lett., 1994
Algorithms for Rapid Computation of Some Distance Functions Between Objects for Path Planning.
Proceedings of the 1994 International Conference on Robotics and Automation, 1994
1993
Proceedings of the 1993 IEEE International Conference on Robotics and Automation, 1993
1992
Proceedings of the Fourth International Conference on Tools with Artificial Intelligence, 1992