K. S. Sainarayanan
According to our database1,
K. S. Sainarayanan
authored at least 8 papers
between 2005 and 2008.
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Bibliography
2008
Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
2007
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2006
A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
2005
A novel deep submicron low power bus coding technique.
Proceedings of the Third IASTED International Conference on Circuits, 2005