K. Rim

According to our database, K. Rim authored at least 6 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Demonstration of Logic-Block Performance-Power Gain by 1st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2nm Node.

H. Fukutome, J. Kim, J. Shin, J. Kim, Y. Lee, Y. Park, D. Oh, S. Chae, B. Eom, YS Nam, M. Lee, S. Ha, EG Chung, J. Kim, M. Jo, SH Lee, S. Kim, KH Cho, KW Lee, DW Kim, HJ Cho, K. Rim, SD Kwon, J. Song

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Device Design and Reliability of GAA MBCFET.

M. Kang, M. Chang, Y. Park, C. Noh, S. H. Hong, B. Park, Y. H. Park, Y. C. Jung, W. S. Lim, G. H. Kim, Y. Lee, H. Yang, D. Shin, J. G. Yang, K. H. Cho, W. C. Jeong, H.-J. Cho, Wook-Hyeon Kwon, D. W. Kim, K. Rim, J. H. Song

Proceedings of the IEEE International Reliability Physics Symposium, 2024

2022

Comprehensive Feasibility Study of Single FIN Transistors for Scaling Both Switching Energy and Device Footprint.

H. Fukutome, K. Suh, W. Kim, Y. Moriyama, S. Kang, B. Eom, J. Kim, C. Yoon, W. Kwon, Y. Chung, Y. Nam, Y. Kim, S. Park, J. Park, H.-J. Cho, K. Rim, S. D. Kwon

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2016

Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes.

Seung Chul Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, Joseph Wang, G. Nallapati, Mustafa Badaroglu, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015

Holistic technology optimization and key enablers for 7nm mobile SoC.

Seung Chul Song, J. Xu, N. N. Mojumder, K. Rim, D. Yang, Jerry Bao, J. Zhu, Joseph Wang, Mustafa Badaroglu, V. Machkaoutsan, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap

Proceedings of the Symposium on VLSI Circuits, 2015

Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization.

N. N. Mojumder, Seung Chul Song, K. Rim, J. Xu, Joseph Wang, J. Zhu, Milena Vratonjic, K. Lin, Martin Saint-Laurent, Paul Bassett, Geoffrey Yeap

Proceedings of the Symposium on VLSI Circuits, 2015