K. Phoa

According to our database, K. Phoa authored at least 2 papers between 2015 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

Transistor reliability characterization and modeling of the 22FFL FinFET technology.

Chen-Yi Su, M. Armstrong, Lei Jiang, S. A. Kumar, C. D. Landon, S. Liu, Inanc Meric, K. W. Park, Leif Paulson, K. Phoa, Bernhard Sell, Jihan Standfest, Ketul B. Sutaria, J. Wan, D. Young, Stephen Ramey

Proceedings of the IEEE International Reliability Physics Symposium, 2018

2015

A 14 nm SoC platform technology featuring 2^nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um² SRAM cells, optimized for low power, high performance and high density SoC products.

Chia-Hong Jan, F. Al-amoody, H.-Y. Chang, T. Chang, Y.-W. Chen, N. Dias, Walid M. Hafez, Doug B. Ingerly, M. Jang, Eric Karl, S. K.-Y. Shi, K. Komeyli, H. Kilambi, A. Kumar, K. Byon, C.-G. Lee, J. Lee, T. Leo, P.-C. Liu, N. Nidhi, R. Olac-vaw, C. Petersburg, K. Phoa, Chetan Prasad, C. Quincy, R. Ramaswamy, T. Rana, L. Rockford, Aravinth Subramaniam, C. Tsai, Peter Vandervoorn, L. Yang, A. Zainuddin, Peng Bai

Proceedings of the Symposium on VLSI Circuits, 2015