K. Najeeb

According to our database, K. Najeeb authored at least 5 papers between 2006 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits.

K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula

J. Low Power Electron., 2007

Power Virus Generation Using Behavioral Models of Circuits.

K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Controllability-driven Power Virus Generation for Digital Circuits.

K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses.

K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam

J. Low Power Electron., 2006

Delay and peak power minimization for on-chip buses using temporal redundancy.

K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006