K. Nagaraj

According to our database, K. Nagaraj authored at least 7 papers between 1980 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2006

Design of Low Power Digital Phase Lock Loops.

K. Nagaraj, N. Nayak

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

2003

Background calibration of operational amplifier gain error in pipelined A/D converters.

Ahmed M. A. Ali, K. Nagaraj

IEEE Trans. Circuits Syst. II Express Briefs, 2003

2001

Background digital error correction technique for pipelined analog-digital converters.

Sameer R. Sonkusale, Jan Van der Spiegel, K. Nagaraj

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Correction of operational amplifier gain error in pipelined A/D converters.

Ahmed M. A. Ali, K. Nagaraj

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1999

Efficient 6-bit A/D converter using a 1-bit folding front end.

K. Nagaraj, F. Chen, T. R. Viswanathan

IEEE J. Solid State Circuits, 1999

1995

Self-Calibration Technique for Pipe-Lined Algorithmic ADC.

K. Nagaraj

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1980

An Inexpensive Automatic Test System for Remote Supervision of Repeatered Lines.

K. Nagaraj, J. K. Verma

IEEE Trans. Commun., 1980