K. Gavaskar
Orcid: 0000-0003-4432-339X
According to our database1,
K. Gavaskar
authored at least 9 papers
between 2019 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2023
New approach for improving the performance of dual axis solar tracker with auto cleaning system.
Soft Comput., December, 2023
Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis.
Wirel. Pers. Commun., March, 2023
Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors.
Wirel. Pers. Commun., 2023
2022
A Variant of Long Multiplication Design with Low Power and Area Using Modified 7: 3 Compressor for Biomedical Applications.
Wirel. Pers. Commun., 2022
A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors.
Wirel. Pers. Commun., 2022
Low Power CMOS Design of Phase Locked Loop for Fastest Frequency Acquisition at Various Nanometer Technologies.
Wirel. Pers. Commun., 2022
Design and comparative analysis of SRAM array using low leakage controlled transistor technique with improved delay.
J. Ambient Intell. Humaniz. Comput., 2022
2019
Wirel. Pers. Commun., 2019
Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories.
Wirel. Pers. Commun., 2019