K. Bharath

According to our database, K. Bharath authored at least 5 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs.

Anirban Sengupta, Rahul Chaurasia, K. Bharath

Comput. Electr. Eng., October, 2023

Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores.

Mahendra Rathor, Aditya Anshul, K. Bharath, Rahul Chaurasia, Anirban Sengupta

Comput. Electr. Eng., January, 2023

2022

Designing Low Cost Secured DSP Core using Steganography and PSO for CE systems.

Aditya Anshul, K. Bharath, Anirban Sengupta

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2017

Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology.

Harsh Rawat, K. Bharath, Alexander Fell

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

2016

Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell.

Pulkit Sharma, R. Anusha, K. Bharath, Jasmine Kaur Gulati, Preet K. Walia, Sumit Jagdish Darak

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016