Jyotsna Chauhan

According to our database, Jyotsna Chauhan authored at least 1 paper in 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2010

Graphene tunneling FET and its applications in low-power circuit design.

Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Mohanram

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010