Jyoti Patel

According to our database, Jyoti Patel authored at least 12 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Statistical inference on multicomponent stress-strength reliability with non-identical component strengths using progressively censored data from Kumaraswamy distribution.

Shubham Saini, Jyoti Patel, Renu Garg

Soft Comput., September, 2024

Aggregation of Constrained Crowd Opinions for Urban Planning.

Akanksha Das, Jyoti Patel, Malay Bhattacharyya

CoRR, 2024

Unveiling Thermal Cross Talk in 5nm Gate-All-Around Stacked Nanosheet FETs: A Machine Learning Perspective.

Vivek Kumar, Nischal Anand, Rohit Rai, Sneha Chauhan, Jyoti Patel

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Interface Trap Analysis in Multi-Fin FinFET Technology: a Crucial Reliability Issue in Digital Application.

Jyoti Patel, Sankalp Rai, Vivek Kumar, Sudeb Dasgupta

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Judgment Analysis in a Streaming Setting Incurring Logarithmic Space of the Annotators.

Jyoti Patel, Soumen Mandal, Malay Bhattacharyya

Proceedings of the Pattern Recognition - 27th International Conference, 2024

Small Signal Analysis of Nanosheet Transistor for sub-THz Frequency Considering Intersheet Capacitances and Modified Admittance Parameters.

Jyoti Patel, Navjeet Bagga, Vivek Kumar, S. Dasgupta

Proceedings of the Device Research Conference, 2024

2023

Dronevision: A Dataset of Aerial Videos for Computer Vision Applications.

Dhrumil Patel, Akshara Mehta, Mallikarjun Bhusnoor, Jyoti Patel, Sandeep Sainkar, Ninad Mehendale

Dataset, May, 2023

FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor.

Vivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Power Efficient Hardware Fingerprint: Exploiting Process-Variations in A Quasi-Planar 14nm FinFET.

Jyoti Patel, Govind Sharma, Chitraja Rajan, Vivek Kumar, Sudeb Dasgupta

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022

Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications.

Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

FEM Modeling of Thermal Aspect of Dielectric Inserted Under Source & Drain of 5 nm Nanosheet.

Vivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2019

Performance improvement of nano wire TFET by hetero-dielectric and hetero-material: At device and circuit level.

Jyoti Patel, Dheeraj Sharma, Shivendra Yadav, Alemienla Lemtur, Priyanka Suman

Microelectron. J., 2019