Jyothi Velamala

According to our database¹, Jyothi Velamala authored at least 16 papers between 2009 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2023

A Physical Unclonable Function Leveraging Hot Carrier Injection Aging.

[BibT_eX]

[DOI]

Rachael J. Parker

Jyothi Bhaskarr Velamala

Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022

PVT Tolerant Zero Bit-Error-Rate Physical Unclonable Function Exploiting Hot Carrier Injection Aging in 7nm FinFET Technology.

[BibT_eX]

[DOI]

Jyothi Bhaskarr Velamala

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2015

Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014

Cross-Layer Modeling and Simulation of Circuit Reliability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2012

A self-tuning design methodology for power-efficient multi-core systems.

[BibT_eX]

[DOI]

Janet Meiling Wang Roveda

ACM Trans. Design Autom. Electr. Syst., 2012

Physics matters: statistical aging prediction under trapping/detrapping.

[BibT_eX]

[DOI]

Jyothi Bhaskarr Velamala

Ketul Sutaria

Takashi Sato

Yu Cao

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Statistical aging under dynamic voltage scaling: A logarithmic model approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Circuit-level delay modeling considering both TDDB and NBTI.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Failure diagnosis of asymmetric aging under NBTI.

[BibT_eX]

[DOI]

Jyothi Bhaskarr Velamala

Venkatesa Ravi

Yu Cao

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Design sensitivity of single event transients in scaled logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

A self-evolving design methodology for power efficient multi-core systems.

[BibT_eX]

[DOI]

Janet Meiling Wang Roveda

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Optimized self-tuning for circuit aging.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

In-situ characterization and extraction of SRAM variability.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

Enabling resonant clock distribution with scaled on-chip magnetic inductors.

[BibT_eX]

[DOI]

Saurabh Sinha

Wei Xu

Jyothi Bhaskarr Velamala

Proceedings of the 27th International Conference on Computer Design, 2009

Circuit aging prediction for low-power operation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Jyothi Velamala

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