Jyoshnavi Akiri

According to our database, Jyoshnavi Akiri authored at least 2 papers between 2021 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology.

Jyoshnavi Akiri, Lean Karlo S. Tolentino, Lung-Jieh Yang, Balasubramanian Esakki, Sivaperumal Sampath, Chua-Chin Wang

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop.

Uday Kiran Naidu Ekkurthi, Venkatesh Dasari, Jyoshnavi Akiri, Chua-Chin Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021