Jyh-Woei Lin

According to our database, Jyh-Woei Lin authored at least 11 papers between 2001 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

Detecting Total Electron Content Precursors Before Earthquakes by Examining Total Electron Content Images Based on Butterworth Filter in Convolutional Neural Networks.

Jyh-Woei Lin, Juing-Shian Chiou

IEEE Access, 2020

2019

Detecting All Possible Ionospheric Precursors by Kernel-Based Two-Dimensional Principal Component Analysis.

Jyh-Woei Lin, Juing-Shian Chiou, Chun-Tang Chao

IEEE Access, 2019

Active Probability Backpropagation Neural Network Model for Monthly Prediction of Probabilistic Seismic Hazard Analysis in Taiwan.

Jyh-Woei Lin, Juing-Shian Chiou

IEEE Access, 2019

2018

Determining Neuronal Number in Each Hidden Layer Using Earthquake Catalogues as Training Data in Training an Embedded Back Propagation Neural Network for Predicting Earthquake Magnitude.

Jyh-Woei Lin, Chun-Tang Chao, Juing-Shian Chiou

IEEE Access, 2018

2012

Ionospheric total electron content anomalies due to Typhoon Nakri on 29 May 2008: A nonlinear principal component analysis.

Jyh-Woei Lin

Comput. Geosci., 2012

Potential reasons for ionospheric anomalies immediately prior to China's Wenchuan earthquake on 12 May 2008 detected by nonlinear principal component analysis.

Jyh-Woei Lin

Int. J. Appl. Earth Obs. Geoinformation, 2012

2011

Is it possible to trace an impending earthquake's occurrence from seismo-ionospheric disturbance using principal component analysis? A study of Japan's Iwate-Miyagi Nairiku earthquake on 13 June 2008.

Jyh-Woei Lin

Comput. Geosci., 2011

2003

A fast locking and low jitter delay-locked loop using DHDL.

Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2003

2002

A wide-range delay-locked loop with a fixed latency of one clock cycle.

Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2002

A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay.

Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

A fast-lock mixed-mode DLL using a 2-b SAR algorithm.

Guang-Kaai Dehng, Jyh-Woei Lin, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2001