Justin S. J. Wong

Orcid: 0000-0002-4378-1199

Affiliations:
  • Imperial College London. UK


According to our database1, Justin S. J. Wong authored at least 22 papers between 2007 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network.
IEEE Trans. Neural Networks Learn. Syst., 2022

2019
A Real-Time Coprime Line Scan Super-Resolution System for Ultra-Fast Microscopy.
IEEE Trans. Biomed. Circuits Syst., 2019

High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing.
J. Imaging, 2019

2017
Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory.
Proceedings of the International Conference on Field Programmable Technology, 2017

2014
Mitigation of process variation effect in FPGAs with partial rerouting method.
IEICE Electron. Express, 2014

Classification on variation maps: a new placement strategy to alleviate process variation on FPGA.
IEICE Electron. Express, 2014

2013
Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Variation and Reliability in FPGAs.
IEEE Des. Test, 2013

Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

A variation-adaptive retiming method exploiting reconfigurability.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
A two-stage variation-aware placement method for FPGAS exploiting variation maps classification.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Improved delay measurement method in FPGA based on transition probability.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Degradation Analysis and Mitigation in FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Degradation in FPGAs: measurement and modelling.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009
Self-Measurement of Combinatorial Circuit Delays in FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2009

2008
Characterisation of FPGA Clock Variability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A transition probability based delay measurement method for arbitrary circuits on FPGAs.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Modelling and compensating for clock skew variability in FPGAs.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Combating process variation on FPGAS with a precise at-speed delay measurement method.
Proceedings of the FPL 2008, 2008

Measuring and modeling FPGA clock variability.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

2007
Self-characterization of Combinatorial Circuit Delays in FPGAs.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007


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