Jürgen Koehl

According to our database, Jürgen Koehl authored at least 12 papers between 1991 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

Considering possible opens in non-tree topology wire delay calculation.

Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

Robust wiring networks for DfY considering timing constraints.

Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

Yield Improvement by Local Wiring Redundancy.

Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller, Sven Peyer, Christian Schulte

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.

Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2003

Designing mega-ASICs in nanogate technologies.

David E. Lackey, Paul S. Zuchowski, Jürgen Koehl

Proceedings of the 40th Design Automation Conference, 2003

IBM's 50 Million gate ASICs.

Jürgen Koehl, David E. Lackey, George W. Doerre

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2001

Automatic Hierarchical Design: Fantasy or Reality? (Panel).

Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000

Platzierungsbasierte Logikoptimierung komplexer VLSI Chips.

Jürgen Koehl, Jürgen Schietke

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

1998

Analysis, reduction and avoidance of crosstalk on VLSI chips.

Tilmann Stöhr, Markus Alt, Asmus Hetzel, Jürgen Koehl

Proceedings of the 1998 International Symposium on Physical Design, 1998

A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset.

Jürgen Koehl, Ulrich Baur, Thomas Ludwig, Bernhard Kick, Thomas Pflueger

Proceedings of the 1998 Design, 1998

1997

Standard-cell-based design methodology for high-performance support chips.

Bernhard Kick, Ulrich Baur, Jürgen Koehl, Thomas Ludwig, Thomas Pflueger

IBM J. Res. Dev., 1997

1991

An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement.

Ren-Song Tsay, Jürgen Koehl

Proceedings of the 28th Design Automation Conference, 1991