Jürgen Becker
Orcid: 0000-0002-5082-5487Affiliations:
- Karlsruhe Institute of Technology, Germany
- Kaiserslautern University of Technology, Germany (PhD 1997)
According to our database1,
Jürgen Becker
authored at least 545 papers
between 1994 and 2024.
Collaborative distances:
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Bibliography
2024
Real-Time Graph Building on FPGAs for Machine Learning Trigger Applications in Particle Physics.
Comput. Softw. Big Sci., December, 2024
Frontiers Big Data, 2024
Work-in-Progress: Real-Time Neural Network Inference on a Custom RISC-V Multicore Vector Processor.
CoRR, 2024
Hybrid Spiking Neural Networks for Low-Power Intra-Cortical Brain-Machine Interfaces.
CoRR, 2024
Low-Power Vibration-Based Predictive Maintenance for Industry 4.0 using Neural Networks: A Survey.
CoRR, 2024
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024
A Dynamically Pipelined Dataflow Architecture for Graph Convolutions in Real-Time Event Interpretation.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024
Scalable Multi-Level Synchronization Technique of Distributed Multi-RFSoC-Server Systems for 6G.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024
Modular Hardware Design for High-Performance MIMO-Capable SDR Systems to Accelerate 6G Development.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024
Work in Progress: Predictable Execution of Isolated Real-Time Tasks on Multicore Systems Using the LET Paradigm.
Proceedings of the 30th IEEE Real-Time and Embedded Technology and Applications Symposium, 2024
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
ICE TEA: Insertion of Custom Early Exits for Time-, Energy- & Anomaly-Aware Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Automated Deep Neural Network Inference Partitioning for Distributed Embedded Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
A Challenge-Based Blended Learning Approach for an Introductory Digital Circuits and Systems Course.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024
Proceedings of the International Conference on Neuromorphic Systems, 2024
Proceedings of the 8th IEEE International Conference on Fog and Edge Computing, 2024
Proceedings of the 15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2024
Enhanced Accelerator Design for Efficient CNN Processing with Improved Row-Stationary Dataflow.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
Proceedings of the 3rd IEEE German Education Conference, GeCon 2024, Munich, 2024
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024
Automated Polyhedron-based TDMA Schedule Design for Predictable Mixed-Criticality MPSoCs.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024
BayWatch: Leveraging Bayesian Neural Networks for Hardware Fault Tolerance and Monitoring.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024
UNCOVER: Data-Driven Design Support through Continuous Monitoring of Security Incidents.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
XANDAR: An X-by-Construction Framework for Safety, Security, and Real-Time Behavior of Embedded Software Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Enhancing Force Sensing Capabilities in Exoskeleton Interfaces Using Compliant Actuator-Sensor Units - A User Study.
Proceedings of the 10th IEEE RAS/EMBS International Conference for Biomedical Robotics and Biomechatronics, 2024
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024
2023
CNNParted: An open source framework for efficient Convolutional Neural Network inference partitioning in embedded systems.
Comput. Networks, June, 2023
Towards the on-device Handwriting Trajectory Reconstruction of the Sensor Enhanced Pen.
Proceedings of the 9th IEEE World Forum on Internet of Things, 2023
Towards Hardware-Software Self-Adaptive Acceleration of Spiking Neural Networks on Reconfigurable Digital Hardware.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy Efficiency.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
European Processor Initiative Demonstration of Integrated Semi-Autonomous Driving System.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Proceedings of the Computer Safety, Reliability, and Security, 2023
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
Automated Replacement of State-Holding Flip-Flops to Enable Non-Volatile Checkpointing.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
Multilevel Security Model for Secure Information Flow Inside Software Components Employing Automated Code Generation.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023
Leveraging Adaptive Redundancy in Multi-Core Processors for Realizing Adaptive Fault Tolerance in Mixed-Criticality Systems.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023
Context-Aware Layer Scheduling for Seamless Neural Network Inference in Cloud-Edge Systems.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
A Unified SoC Lab Course: Combined Teaching of Mixed Signal Aspects, System Integration, Software Development and Documentation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Smart Cities Conference, 2023
Policy-Based Task Allocation at Runtime for a Self-Adaptive Edge Computing Infrastructure.
Proceedings of the 15th IEEE International Symposium on Autonomous Decentralized System, 2023
Design Space Exploration on Efficient and Accurate Human Pose Estimation from Sparse IMU-Sensing.
IROS, 2023
Proceedings of the IEEE International Conference on Internet of Things and Intelligence Systems, 2023
EFFECT: An End-to-End Framework for Evaluating Strategies for Parallel AI Anomaly Detection.
Proceedings of the International Neural Network Society Workshop on Deep Learning Innovations and Applications, 2023
A Hardware-Aware Sampling Parameter Search for Efficient Probabilistic Object Detection.
Proceedings of the Computer Vision Systems: 14th International Conference, 2023
Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, 2023
An Analytical Model of Configurable Systolic Arrays to find the Best-Fitting Accelerator for a given DNN Workload.
Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, 2023
SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
ReLoDAQ: Resource-Efficient, Low-Overhead 200 Gbits<sup>-1</sup> Data Acquisition System for 6G Prototyping.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023
LETSCOPE: Lifecycle Extensions Through Software-Defined Predictive Control of Power Electronics.
Proceedings of the 20th IEEE International Conference on Smart Technologies, 2023
Work-in-Progress: Integrating WebAssembly into Service-Oriented Architectures for Edge Systems.
Proceedings of the International Conference on Embedded Software, 2023
Mitigating Masking in Automotive Communication Systems: Modeling and Hardware Generation.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Automatic Deployment of Embedded Real-Time Software Systems to Hypervisor-Managed Platforms.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
A Scalable and Cost-Efficient Antenna Testbed Using FPGA-Server Compound Structures for Prototyping 6G Applications.
Proceedings of the 19th International Conference on Distributed Computing in Smart Systems and the Internet of Things, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the IEEE Intl Conf on Dependable, 2023
A Convolution Neural Network Based Displaced Vertex Trigger for the Belle II Experiment.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023
A Hardware-Centric Approach to Increase and Prune Regular Activation Sparsity in CNNs.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
The impact of formulation of cost function in Task Mapping Problem on NoCs using bio-inspired based-metaheuristics.
Microprocess. Microsystems, October, 2022
V-FPGAs: Increasing Performance with Manual Placement, Timing Extraction and Extended Timing Modeling.
J. Signal Process. Syst., 2022
Frontiers Big Data, 2022
Lifecycle Management of Automotive Safety-Critical Over the Air Updates: A Systems Approach.
IEEE Access, 2022
XANDAR: A holistic Cybersecurity Engineering Process for Safety-critical and Cyber-physical Systems.
Proceedings of the 95th IEEE Vehicular Technology Conference, 2022
Hypervisor-Based Target Deployment Strategies for Time Predictability in Model-Based Development.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Using Trace Data for Run-Time Optimization of Parallel Execution in Real-Time Multi-Core Systems.
Proceedings of the 28th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2022
Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2022
Hardware-aware Workload Distribution for AI-based Online Handwriting Recognition in a Sensor Pen.
Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022
Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGA.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022
Proceedings of the 8th International Conference on Information Systems Security and Privacy, 2022
A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware accelerators.
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022
Proceedings of the 26th IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, 2022
Hardware Support for Predictable Resource Sharing in Virtualized Heterogeneous Multicores.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Adaptive Exploration Based Routing for Spatial Isolation in Mixed Criticality Systems.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Hardware-aware Partitioning of Convolutional Neural Network Inference for Embedded AI Applications.
Proceedings of the 18th International Conference on Distributed Computing in Sensor Systems, 2022
XANDAR: Exploiting the X-by-Construction Paradigm in Model-based Development of Safety-critical Systems.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Achieving cost-efficient fail-operational behavior based on inherent redundancy at the system level.
Microprocess. Microsystems, November, 2021
Model-based configuration of access protection units for multicore processors in embedded systems.
Microprocess. Microsystems, November, 2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Utilizing and Extending Trusted Execution Environment in Heterogeneous SoCs for a Pay-Per-Device IP Licensing Scheme.
IEEE Trans. Inf. Forensics Secur., 2021
From MOSFETs to Ambipolar Transistors: Standard Cell Synthesis for the Planar RFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Computers, 2021
A Hybrid Prototyping Framework in a Virtual Platform Centered Design and Verification Flow.
IEEE Embed. Syst. Lett., 2021
Evaluation of a Hypervisor-Based Smart Controller for Industry 4.0 Functions in Manufacturing.
Proceedings of the 7th IEEE World Forum on Internet of Things, 2021
FLECSim-SoC: A Flexible End-to-End Co-Design Simulation Framework for System on Chips.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021
Ant Colony Optimization Based NoCs for Flexible Spatial Isolation in Mixed Criticality Systems.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2021
Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2021
Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2021
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Proceedings of the IEEE International Symposium on Systems Engineering, 2021
Proceedings of the IEEE International Symposium on Systems Engineering, 2021
Proceedings of the 19th IEEE International Conference on Industrial Informatics, 2021
Binary-LoRAX: Low-Latency Runtime Adaptable XNOR Classifier for Semi-Autonomous Grasping with Prosthetic Hands.
Proceedings of the IEEE International Conference on Robotics and Automation, 2021
Neuromorphic Vision mit Spiking Neural Networks zur Sturzerkennung im betreuten Wohnen.
Proceedings of the 51. Jahrestagung der Gesellschaft für Informatik, INFORMATIK 2021 - Computer Science & Sustainability, Berlin, Germany, 27. September, 2021
XANDAR: X-by-Construction Design framework for Engineering Autonomous & Distributed Real-time Embedded Software Systems.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board Networks.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGA.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021
Moving Target and Implementation Diversity Based Countermeasures Against Side-Channel Attacks.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021
2020
Proceedings of the 12th IEEE International Workshop on Information Forensics and Security, 2020
Embedded Image Processing the European Way: A new platform for the future automotive market.
Proceedings of the 6th IEEE World Forum on Internet of Things, 2020
Linking Intrusion Detection System Information and System Model to Redesign Security Architecture.
Proceedings of the IEEE International Systems Conference, 2020
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, 2020
A Study of the Impact of Formulation of Cost Function in Task Mapping Problem on NoCs.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020
Towards Ambipolar Planar Devices: The DeFET Device in Area Constrained XOR Applications.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Towards an On-Demand Redundancy Concept for Autonomous Vehicle Functions using Microservice Architecture.
Proceedings of the IEEE International Symposium on Systems Engineering, 2020
An Architecture-based Modeling Approach Using Data Flows for Zone Concepts in Industry 4.0.
Proceedings of the IEEE International Symposium on Systems Engineering, 2020
Proceedings of the IEEE International Symposium on Systems Engineering, 2020
Designing Universal Logic Module FPGA Architectures for Use With Ambipolar Transistor Technology.
Proceedings of the International Conference on Field-Programmable Technology, 2020
An Approach to Cost-Efficient Fault Tolerance in Inherently Redundant Fail-Operational Systems.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
A Formal Model for the Automatic Configuration of Access Protection Units in MPSoC-Based Embedded Systems.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
WCET-aware Code Generation and Communication Optimization for Parallelizing Compilers.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications.
J. Aerosp. Inf. Syst., November, 2019
Cross-Layer Behavioral Modeling and Simulation of E/E-Architectures using PREEvision and Ptolemy II.
Simul. Notes Eur., 2019
An Efficient High-Throughput Generic QAM Transmitter with Scalable Spiral FIR Filter.
J. Circuits Syst. Comput., 2019
Model-Driven Design of Tools for Multi-Domain Systems with Loosely Coupled Metamodels.
Proceedings of the 2019 IEEE International Systems Conference, 2019
A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Reliable Fail-Operational Automotive E/E-Architectures by Dynamic Redundancy and Reconfiguration.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019
Proceedings of the 5th International Conference on Information Systems Security and Privacy, 2019
Proceedings of the International Conference on Field-Programmable Technology, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019
Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
ACM Trans. Embed. Comput. Syst., 2018
A Content - Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
Data Readout Triggering for Phase 2 of the Belle II Particle Detector Experiment Based on Neural Networks.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018
Dynamic Reconfiguration for Real-Time Automotive Embedded Systems in Fail-Operational Context.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018
A WCET-aware parallel programming model for predictability enhanced multi-core architectures.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
The ARAMiS Project Initiative - Multicore Systems in Safety- and Mixed-Critical Applications.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
Proceedings of the Advances in Aeronautical Informatics, Technologies Towards Flight 4.0., 2018
2017
J. Signal Process. Syst., 2017
Efficient task spawning for shared memory and message passing in many-core architectures.
J. Syst. Archit., 2017
Proceedings of the 40th International Conference on Telecommunications and Signal Processing, 2017
Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017
2016
IEEE Trans. Parallel Distributed Syst., 2016
Int. J. Online Eng., 2016
A variable FPGA based generic QAM transmitter with scalable mixed time and frequency domain signal processing.
Proceedings of the 39th International Conference on Telecommunications and Signal Processing, 2016
Tutorial 3A: Bringing cores closer together: The wireless revolution in on-chip communication.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016
A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016
Programmable Logic as Device Virtualization Layer in Heterogeneous Multicore Architectures.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016
2015
Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures.
Microprocess. Microsystems, 2015
Parallelization of genetic algorithms for sorting permutations by reversals over biological data.
Int. J. Hybrid Intell. Syst., 2015
A V2X message evaluation methodology and cross-domain modelling of safety applications in V2X-enabled E/E-architectures.
Proceedings of the 8th International Conference on Simulation Tools and Techniques, 2015
Proceedings of the 10th IEEE International Symposium on Industrial Embedded Systems, 2015
Design of an embedded UWB hardware platform for navigation in GPS denied environments.
Proceedings of the 2015 IEEE Symposium on Communications and Vehicular Technology in the Benelux, 2015
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Designing applications for heterogeneous many-core architectures with the FlexTiles Platform.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015
Parametric design space exploration for optimizing QAM based high-speed communication.
Proceedings of the 2015 IEEE/CIC International Conference on Communications in China, 2015
Software-in-the-Loop simulation of embedded control applications based on Virtual Platforms.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Power Estimation of an ECDSA Core Applied in V2X Scenarios Using Heterogeneous Distributed Simulation.
Proceedings of the 19th IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, 2015
Proceedings of the 19th IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, 2015
Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on Chip.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015
Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015
2014
A comprehensive comparison of GPU- and FPGA-based acceleration of reflection image reconstruction for 3D ultrasound computer tomography.
J. Real Time Image Process., 2014
GPU-based iterative transmission reconstruction in 3D ultrasound computer tomography.
J. Parallel Distributed Comput., 2014
Evaluation of performance and architectural efficiency of FPGAs and GPUs in the 40 and 28 nm generations for algorithms in 3D ultrasound computer tomography.
Comput. Electr. Eng., 2014
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014
Enabling partial reconfiguration for coprocessors in mixed criticality multicore systems using PCI express single-root I/O virtualization.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
Architectural measures against radiation effects in multicore SoC for safety critical applications.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014
Virtualization Support for FPGA-Based Coprocessors Connected via PCI Express to an Intel Multicore Platform.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
Proceedings of the International Conference on Computing, Networking and Communications, 2014
A flexible interface architecture for reconfigurable coprocessors in embedded multicore systems using PCIe Single-root I/O virtualization.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
Ultra-dense, single-wavelength DFT-spread OFDM PON with laserless 1 Gb/s ONU at only 300 MBd per spectral group.
Proceedings of the European Conference on Optical Communication, 2014
Adaptive Algorithm and Tool Flow for Accelerating System C on Many-Core Architectures.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Hardware virtualization support for shared resources in mixed-criticality multicore systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Flexible real-time transmitter at 10 Gbit/s for SCFDMA PONs focusing on low-cost ONUs.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure.
Proceedings of the ARCS 2014, 2014
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014
2013
ACM Trans. Reconfigurable Technol. Syst., 2013
ACM Trans. Reconfigurable Technol. Syst., 2013
MORPHEUS: A heterogeneous dynamically reconfigurable platform for designing highly complex embedded systems.
ACM Trans. Embed. Comput. Syst., 2013
ACM Trans. Embed. Comput. Syst., 2013
ACM Trans. Embed. Comput. Syst., 2013
Microprocess. Microsystems, 2013
Colorless FDMA-PON With Flexible Bandwidth Allocation and Colorless, Low-Speed ONUs [Invited].
JOCN, 2013
it Inf. Technol., 2013
Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011).
Int. J. Reconfigurable Comput., 2013
Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011).
Int. J. Reconfigurable Comput., 2013
Providing multiple hard latency and throughput guarantees for packet switching networks on chip.
Comput. Electr. Eng., 2013
A SystemC modeling and simulation methodology for fast and accurate parallel MPSoC simulation.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 28th Annual ACM Symposium on Applied Computing, 2013
Improving parallel MPSoC simulation performance by exploiting dynamic routing delay prediction.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
A flexible implementation of the PSO algorithm for fine- and coarse-grained reconfigurable embedded systems.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Flexible WDM-PON with Nyquist-FDM and 31.25 Gbit/s per wavelength channel using colorless, low-speed ONUs.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
Parallelization and virtualization of genetic algorithms for sorting permutations by reversals.
Proceedings of the Fifth World Congress on Nature and Biologically Inspired Computing, 2013
LImbiC: An adaptable architecture description language model for developing an application-specific image processor.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the 2013 International Symposium on System on Chip, 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Simplify: A Framework for Enabling Fast Functional/Behavioral Validation of Multiprocessor Architectures in the Cloud.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Development and Evaluation of Distributed Simulation of Embedded Systems Using Ptolemy and HLA.
Proceedings of the 17th IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, 2013
AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Concurrent Error Detection in Multipliers by Using Reduced Wordlength Multiplication and Logarithms.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture.
Int. J. Reconfigurable Comput., 2012
Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices.
Int. J. Reconfigurable Comput., 2012
Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels.
Int. J. Reconfigurable Comput., 2012
Int. J. Reconfigurable Comput., 2012
Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration.
Int. J. Reconfigurable Comput., 2012
A Framework for exploration of parallel SystemC simulation on the single-chip cloud computer.
Proceedings of the International ICST Conference on Simulation Tools and Techniques, 2012
LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012
Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
A flexible approach for compiling scilab to reconfigurable multi-core embedded systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Comparison of processing performance and architectural efficiency metrics for FPGAs and GPUs in 3D Ultrasound Computer Tomography.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Proceedings of the 2012 International Symposium on System on Chip, 2012
A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Framework for dynamic verification of multi-domain virtual platforms in industrial automation.
Proceedings of the IEEE 10th International Conference on Industrial Informatics, 2012
Proceedings of the International Conference on Computing, Networking and Communications, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012
Proceedings of the 1st Conference on Embedded Systems, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012
Proceedings of the International Multi-Conference on Systems, Signals & Devices, 2012
Proceedings of the International Multi-Conference on Systems, Signals & Devices, 2012
2011
Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs.
Int. J. Reconfigurable Comput., 2011
Int. J. Reconfigurable Comput., 2011
Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010).
Int. J. Reconfigurable Comput., 2011
Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems.
Int. J. Reconfigurable Comput., 2011
Int. J. Reconfigurable Comput., 2011
Int. J. Reconfigurable Comput., 2011
Int. J. Reconfigurable Comput., 2011
Int. J. Reconfigurable Comput., 2011
HoneyComb: A multi-grained dynamically reconfigurable runtime adaptive hardware architecture.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Proceedings of the 4th International ICST Conference on Simulation Tools and Techniques, 2011
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Using dynamic partial reconfiguration to detect sees in microprocessors through non-intrusive hybrid technique.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
An approach for power and performance evaluation of reconfigurable SoC at mixed abstraction levels.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Power and performance optimization through MPI supported dynamic voltage and frequency scaling.
Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Increasing energy efficiency of automotive E/E-architectures with Intelligent Communication Controllers for FlexRay.
Proceedings of the 2011 International Symposium on System on Chip, 2011
Digital On-demand Computing Organism - Interaction between Monitoring and Middleware.
Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Online Routing of FPGA Clock Networks for Module Relocation in Partial Reconfigurable Multi Clock Designs.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Hyperelliptic Curve Cryptoarchitecture for Fast Execution of Schnorr and Okamoto Authentication Protocols.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Ansätze zur Integration von energieeffizienten Intelligenten Kommunikationskontrollern für FlexRay in Autosar.
Proceedings of the 41. Jahrestagung der Gesellschaft für Informatik, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011
Proceedings of the Organic Computing - A Paradigm Shift for Complex Systems, 2011
2010
ACM Trans. Reconfigurable Technol. Syst., 2010
Message Passing Interface support for the runtime adaptive multi-processor system-on-chip RAMPSoC.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
ISRC: a runtime system for heterogeneous reconfigurable architectures.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/ Virtex II-Pro FPGAs: A Case Study of Distributed Power Management.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
A Secure Keyflashing Framework for Access Systems in Highly Mobile Devices.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
Impact of Task Distribution, Processor Configurations and Dynamic Clock Frequency Scaling on the Power Consumption of FPGA-based Multiprocessors.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
ECDSA Signature Processing over Prime Fields for Reconfigurable Embedded Systems.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
First Evaluation of FPGA Reconfiguration for 3D Ultrasound Computer Tomography.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems Through Dynamic and Partial Reconfiguration: The RAMPSoC Approach.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
FPGA-Based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
A flexible integrated cryptoprocessor for authentication protocols based on hyperelliptic curve cryptography.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
CAP-OS: Operating system for runtime scheduling, task mapping and resource management on reconfigurable multiprocessor architectures.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010
A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010
Performance, accuracy, power consumption and resource utilization analysis for hardware / software realized Artificial Neural Networks.
Proceedings of the Fifth International Conference on Bio-Inspired Computing: Theories and Applications, 2010
Development and Synthesis of Adaptive Multi-grained Reconfigurable Hardware Architecture for Dynamic Function Patterns.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010
Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010
2009
Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems.
Microprocess. Microsystems, 2009
Adaptive real-time image processing exploiting two dimensional reconfigurable architecture.
J. Real Time Image Process., 2009
An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing.
Int. J. Reconfigurable Comput., 2009
Int. J. Reconfigurable Comput., 2009
Proceedings of the 69th IEEE Vehicular Technology Conference, 2009
Method for improving performance in online routing of reconfigurable nano architectures.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Testing of an FPGA Based C2X-Communication Prototype with a Model Based Traffic Generation.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009
Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Adaptive Multicore Systems-on-Chip (MSoC) - Design and Computing in the Nano Era.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.
Proceedings of the Reconfigurable Computing: Architectures, 2009
2008
IEEE Des. Test Comput., 2008
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
A Prototype of Trusted Platform Functionality on Reconfigurable Hardware for Bitstream Updates.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
A self adaptive interfacing concept for consumer device integration into automotive entities.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization.
Proceedings of the FPL 2008, 2008
New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach.
Proceedings of the FPL 2008, 2008
A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput.
Proceedings of the FPL 2008, 2008
Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008
Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2008
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms.
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor.
Proceedings of the Design, Automation and Test in Europe, 2008
Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems.
Proceedings of the Design, Automation and Test in Europe, 2008
A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA.
Proceedings of the Architecture of Computing Systems, 2008
Proceedings of the Reconfigurable Computing: Architectures, 2008
2007
New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur).
it Inf. Technol., 2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Proceedings of the FPL 2007, 2007
On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project.
Proceedings of the FPL 2007, 2007
Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs.
Proceedings of the FPL 2007, 2007
Proceedings of the FPL 2007, 2007
H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture.
Proceedings of the FPL 2007, 2007
Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications.
Proceedings of the FPL 2007, 2007
2006
On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Communication concept for adaptive intelligent run-time systems supporting distributed reconfigurable embedded systems.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006
Proceedings of the ARCS 2006, 2006
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006
Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
2005
it Inf. Technol., 2005
Int. J. Embed. Syst., 2005
Realtime configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation.
Int. J. Embed. Syst., 2005
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Hardware/Software Co-Training Lab: From VHDL Bit-Level Coding up to CASE-Tool Based System Modeling.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005
Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 2005 International Symposium on System-on-Chip, 2005
Proceedings of the 2005 International Symposium on System-on-Chip, 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005
2004
it Inf. Technol., 2004
Coarse-grain reconfigurable XPP devices for adaptive high-end mobile video-processing.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
Formale Verifikation eines Sonet/SDH Framers.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
CARUSO - An Approach Towards a Network of Low Power Autonomic Systems on Chips for Embedded Real-time Application.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
Proceedings of the 34. Jahrestagung der Gesellschaft für Informatik, 2004
On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities.
Proceedings of the Field Programmable Logic and Application, 2004
Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures.
Proceedings of the Field Programmable Logic and Application, 2004
Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems.
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the 2004 Design, 2004
Aufbau- und Strukturkonzepte einer adaptive multigranularen rekonfigurierbaren Hardwarearchitektur.
Proceedings of the ARCS 2004, 2004
2003
Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003
Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the VLSI-SOC: From Systems to Chips, 2003
Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC).
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
PACT XPP Architecture in Adaptive System-on-Chip Integration.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003
An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration.
Proceedings of the 2003 Design, 2003
2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2001
A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication.
J. Supercomput., 2001
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001
Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001
Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design.
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001
Distributed Collaborative Design over Cave2 Framework.
Proceedings of the SOC Design Methodologies, 2001
On the numerical accuracy of CORDIC-based frequency offset compensation in burst oriented OFDM systems.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures.
Proceedings of the Field-Programmable Logic and Applications, 2001
2000
Synthese von Kommunikationsstrukturen und architekturgenaues Rapid-Prototyping eingebetteter Echtzeitsysteme (Communication Synthesis and Architecture-Precise Rapid Prototyping of Embedded systems with Hard Real-Time Constraints).
Informationstechnik Tech. Inform., 2000
Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems.
Des. Autom. Embed. Syst., 2000
An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000
Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000
Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000
IP-based Application Mapping Techniques for Dynamically Reconfigurable Hardware Architectures.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000
Communication Performance Estimation and Communication Synthesis for Architecture-precise Prototyping of Real-time Embedded Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000
Field Programmable Communication Emulation and Optimization for Embedded System Design.
Proceedings of the Field-Programmable Logic and Applications, 2000
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications.
Proceedings of the Field-Programmable Logic and Applications, 2000
Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000
A dynamically reconfigurable system-on-a-chip architecture for future mobile digital signal processing.
Proceedings of the 10th European Signal Processing Conference, 2000
1999
Object-oriented Specification Approach for Synthesis of Hardware-/Software Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1999
ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect.
Proceedings of the VLSI: Systems on a Chip, 1999
Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999
Parallel Hardware Compilation in Complex Hardware/Software Systems based on High-Level Code Transformations.
Proceedings of the Architektur von Rechensystemen, Systemarchitektur auf dem Weg ins 3. Jahrtausend: Neue Strukturen, Konzepte, Verfahren und Bewertungsmethoden, 1999
1998
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998
A Reconfigurable Hardware-Monitor for Communication Analysis in Distributed Real-Time Systems.
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998
Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998
An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications.
Proceedings of the Field-Programmable Logic and Applications, 1998
Proceedings of the Field-Programmable Logic and Applications, 1998
HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998
Proceedings of the ASP-DAC '98, 1998
1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators.
Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997
Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997
A Novel Universal Sequencer Hardware.
Proceedings of the Architektur von Rechensystemen, Arbeitsteilige Systemarchitekturen: Konzepte, Lösungen, Anwendungen, Trends, 1997
PhD thesis, 1997
1996
Concurr. Pract. Exp., 1996
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
Proceedings of IPPS '96, 1996
Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view.
Proceedings of the Field-Programmable Logic, 1996
Proceedings of the Eighth Euromicro Workshop on Real-Time Systems, 1996
Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), 1996
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine.
Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996
1995
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995
1994
Proceedings of the Field-Programmable Logic, 1994