Junyi Luo
Orcid: 0009-0000-0578-2206
According to our database1,
Junyi Luo
authored at least 6 papers
between 2017 and 2024.
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Bibliography
2024
Design of a broadband high-efficiency power amplifier based on continuous class-EF mode.
IEICE Electron. Express, 2024
2023
An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
2022
A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022
A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2020
Proceedings of the 58th Annual Meeting of the Association for Computational Linguistics, 2020
2017
Adaptability-oriented hierarchical correlation optimisation in product family design.
Int. J. Comput. Sci. Math., 2017