Junyan Ren

Orcid: 0000-0002-7799-6251

According to our database1, Junyan Ren authored at least 208 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A 3.0-V 4.2-μA 2.23-ppm/°C BGR with cross-connected NPNs and base-current compensation.
Microelectron. J., 2024

Hardware-Implemented Calibration Based on Sinusoidal Fitting for Hybrid Pipeline ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
28-nm CMOS Ultrasound AFE With Split Attenuation for Optimizing Gain-Range, Noise, and Area.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Low-Noise Low-Power Ultrasound AFE With Continuous TGC Built in Both TIA and Beamformer.
IEEE Trans. Biomed. Circuits Syst., October, 2023

A 90- to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor.
Int. J. Circuit Theory Appl., April, 2023

A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023

A 400-MS/s 12-bit Voltage-Time Hybrid ADC with a Ping-Pong SAR TDC for Speed Enhancement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 300MS/s 57.6dB SNDR Single-Channel SAR ADC with Accelerated SAR Logic.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Three-stage Analog Low-Frequency Drift Calibration and DC Offset Correction Circuit for Ultrasonic AFE.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A 15GHz Class-C VCO with Two-stage Buffer in 0.15-μm GaAs.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Multi-channel 12-bits 100MS/s SAR ADC in 65nm CMOS.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
A 6.5-mm<sup>2</sup> 10.5-to-15.5-GHz Differential GaN PA With Coupled-Line-Based Matching Networks Achieving 10-W Peak P<sub>sat</sub> and 42% PAE.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Sensitivity - Bandwidth Optimization of PMUT with Acoustical Matching Using Finite Element Method.
Sensors, 2022

A 23- to 28-GHz 5-bit switch-type phase shifter with 1-bit calibration based on optimized ABCD matrix design methods for 5G MIMO system in 0.15-μm GaAs.
Int. J. Circuit Theory Appl., 2022

A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology.
Int. J. Circuit Theory Appl., 2022

A 134-154 GHz Low-Noise Amplifier Achieving 36.3-dB Maximum Gain with 3.8-dB Minimum Noise Figure for D-Band Imaging System.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A Broadband LMS-based Band-split Crosstalk Cancellation Method for Ultrasound Systems.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A Branch-Gain-Balanced LNA Based on Voltage- Controlled Resistor Feedback and Shared CMFB Amplifier.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A Single-Channel 1.25-GS/s 11-bit Pipelined ADC with Robust Floating-Powered Ring Amplifier and First-Order Gain Error Calibration.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A Two-Way Current-Combining W-band Power Amplifier Achieving 17.4-dBm Output Power with 19.4% PAE in 65-nm Bulk CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 500-MS/s 9-Bit Time-Domain ADC Using a Nonbinary Successive Approximation TDC.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

A Low Noise TIA with Continuous Time-Gain Compensation for Ultrasound Transducers.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
A 5G Wireless Event-Driven Sensor Chip for Online Power-Line Disturbances Detecting Network in 0.25 μm GaAs Process.
IEEE Trans. Ind. Electron., 2021

A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Development of Broadband High-Frequency Piezoelectric Micromachined Ultrasonic Transducer Array.
Sensors, 2021

A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET.
IEEE Access, 2021

A 120-150 GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm P<sub>sat</sub> for Sub-THz Imaging System.
IEEE Access, 2021

Analysis and Design of a 35-GHz Hybrid π-Network High-Gain Phase Shifter With 360° Continuous Phase Shifting.
IEEE Access, 2021

A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS.
IEEE Access, 2021

Additive Neural Network Based Static and Dynamic Distortion Modeling for Prior-Knowledge-Free Nyquist ADC Characterization.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A Novel Ring Amplifier with Low Common-Mode Voltage Variation and Noise Reduction Using Floating Power Technique.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A Hardware-Efficient Calibrator for SAR-Pipelined ADCs with a Layer-based Sharing Neural Network.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration.
Proceedings of the 18th International SoC Design Conference, 2021

Resistive Degeneration Linearization Dynamic Residue Amplifiers for Pipelined ADCs.
Proceedings of the 18th International SoC Design Conference, 2021

A High Linearity Bootstrapped Switch with Leakage Current Suppressed for GS/s Sampling Rate ADC.
Proceedings of the 18th International SoC Design Conference, 2021

An 11-Bit 500 MS/s Two-Step SAR ADC with Non-Attenuated Passive Residue Transfer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Partially Binarized and Fixed Neural Network Based Calibrator for SAR-Pipelined ADCs Achieving 95.0-dB SFDR.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio.
Proceedings of the 47th ESSCIRC 2021, 2021

A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A 68.36 dB 12 bit 100MS/s SAR ADC with a low-noise comparator in 14-nm CMOS FinFet.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A C-Band Power Amplifier with Over-Neutralization Technique and Coupled-Line MCR Matching Methods for 5G Communication in 0.25-μm GaAs.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A 5-bit High-Linearity, Binary-Recombination-Redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

An 4<sup>th</sup>-order N-path Bandpass Filter with a Tuning Range of 1-30 GHz and OOB Rejection > 30 dB in 28 nm CMOS.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A Three-Stage Comparator with High Speed and Low Power.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A Wide-Range 12b 150MS/s P-SAR ADC with Open-Loop Residue Amplifier for Ultrasound AFE.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A High Linearity and Low Noise Anti-Aliasing Filter for ADCs.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A 79GHz 5-bit Phase Shifter With π-Network in 28-nm CMOS.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC.
IEEE Access, 2020

Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS<sub>2</sub> Materials With Physical and SPICE Model.
IEEE Access, 2020

A 10-18 GHz GaN Power Amplifier Based on Asymmetric Magnetically Coupled Resonator.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A 12-bit SAR ADC Using Pseudo-Dynamic Weighting C-DAC for Capacitor Error Calibration.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A Fast Response Reference Voltage Buffer for 12b 200MS/s SAR ADC.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A 13 Bit 100 MS/s SAR ADC with 74.57 dB SNDR in 14-nm CMOS FinFET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

An Area-Power-Efficient AFE with NS-SAR ADC For High-Frequency Ultrasound Applications.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

A Low-Power Low-Noise Dynamic Comparator With Latch-Embedding Floating Amplifier.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

A Low Power Reference Voltage Buffer and High Density Unit capacitor in a 12b 200MS/s SAR ADC.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

A Calibration Scheme for Nonlinearity of the SAR-Pipelined ADCs Based on a Shared Neural Network.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019
A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

3D FEM Analysis of High-Frequency AlN-Based PMUT Arrays on Cavity SOI.
Sensors, 2019

A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic.
Microelectron. J., 2019

A Ring Amplifier Based Current Feedback Continuous Time PGA for High Frequency Ultrasound Applications.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A 140 GHz, 4 dB Noise-Figure Low-Noise Amplifier Design with the Compensation of Parasitic Capacitance CGS.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Band-Pass Noise-Shaping Modulator Using the Error-Feedback Structure on a 10-bit SAR ADC.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A 20MHz Bandwidth Band-Pass Noise-Shaping SAR ADC With OPAMP Sharing Switched-Capacitor Filter.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Energy-Efficient Analog Frond-End Design for Ultrasound Imaging Applications.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Novel Nauta Transconductor for Ultra-Wideband gm-C Filter with Temperature Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Capacitively-Degenerated High-Linearity Dynamic Amplifier using a Real-Time Gain Detection Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 13-bit 180-MS/s SAR ADC with Efficient Capacitor-Mismatch Estimation and Dither Enhancement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 130-150 GHz Power Amplifier for Millimeter Wave Imaging in 65-nm CMOS.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 Transistors.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A 36-40 GHz VCO with bonding inductors for millimeter wave 5G Communication.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A 22-40.5 GHz UWB LNA Design in 0.15um GaAs.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Comparator-Reused Dynamic-Amplifier for Noise-Shaping SAR ADC.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A 40Gb/s Low Power Transmitter with 2-tap FFE and 40: 1 MUX in 28nm CMOS Technology.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A 5-to-8-GHz Wideband Miniaturized Dielectric Spectroscopy Chip With $I/Q$ Mismatch Calibration in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration.
Microelectron. J., 2018

Low Power Low Noise Amplifier with DC Offset Correction at 1 V Supply Voltage for Ultrasound Imaging Systems.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A Third-order Band-pass Fully-passive Noise-Shaping Modulator Based on a Time-interleaved SAR ADC.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A 12-Bit ENOB 8MHz BW Noise-Shaping SAR ADC Using High-Speed Switches.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching.
IEEE Trans. Very Large Scale Integr. Syst., 2017

An improved ring amplifier with process- and supply voltage-insensitive dead-zone.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

High speed digital ELD compensation with hybrid thermometer coding in CT ΔΣ modulators.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

A stacked-packaged 16-channel ADC for ultrasound application.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 12bit asynchronous SAR-incremental sub-range ADC.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 0.87 mW 7MHz-BW 76dB-SNDR passive noise-shaping modulator based on a SAR ADC.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

An input buffer for 12bit 2GS/s ADC.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A proved dither-injection method for memory effect in double sampling pipelined ADC.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Transformer-based varactor-less 96GHz-110GHz VCO and 89GHz-101GHz QVCO in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
An ARMA-Model-Based NTF Estimation on Continuous-Time ΔΣ Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A Monolithic Sub-sampling PLL based 6-18 GHz Frequency Synthesizer for C, X, Ku Band Communication.
IEICE Trans. Electron., 2015

Greedy Approach Based Heuristics for Partitioning Sparse Matrices.
IEICE Trans. Inf. Syst., 2015

A high power-efficient LVDS output driver with adjustable feed-forward capacitor compensation.
IEICE Electron. Express, 2015

Switch-back based on charge equalization switching technique for SAR ADC.
IEICE Electron. Express, 2015

A 270-MS/s 6-b SAR ADC with preamplifier sharing and self-locking comparators.
IEICE Electron. Express, 2015

Greedy approach based heuristics for partitioning SpMxV on FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system.
Proceedings of the ESSCIRC Conference 2015, 2015

A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

I/Q imbalance estimation in OFDM systems.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A 100MS/s 5bit fully digital flash ADC with standard cells.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

LVDS transmitter with optimized high power-efficiency 8: 1 MUX.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 42fJ 8-bit 1.0-GS/s folding and interpolating ADC with 1GHz signal bandwidth.
IEICE Electron. Express, 2014

A 7 bit 1 GS/s pipelined folding and interpolating ADC with <i>coarse-stage-free joint encoding</i>.
IEICE Electron. Express, 2014

An overview of new design techniques for high performance CMOS millimeter-wave circuits.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

No zero padded sparse matrix-vector multiplication on FPGAs.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

A 131.5GHz, -84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS.
Proceedings of the ESSCIRC 2014, 2014

General expression based inner loop unrolling scheme for TV-GD algorithm adopted in photoacoustic imaging.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013
Carrier Frequency Offset and I/Q Imbalance Compensation for MB-OFDM Based UWB System.
Wirel. Pers. Commun., 2013

A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 96-GHz Oscillator by High-Q Differential Transmission Line loaded with Complementary Split-Ring Resonator in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 0.13-µm CMOS 0.1-12GHz active balun-LNA for multi-standard applications.
IEICE Electron. Express, 2013

A mixed sample-time error calibration technique in time-interleaved ADCs.
IEICE Electron. Express, 2013

Beyond-one-cycle loop delay CT ΔΣ modulators with proper rational NTF synthesis and time-interleaved quantizers.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Power efficient SAR ADC with optimized settling technique.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A 80-dB DR, 10-MHz BW continuous-time sigma-delta modulator with low power comparators and switch drivers.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A DLL based low-phase-noise clock multiplier with offset-tolerant PFD.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

FFT design for OFDM-based cognitive radio using a reconfigurable baseband processing architecture.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Automatic gain control algorithm with high-speed and double closed-loop in UWB system.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Low-complexity synchronizer used in DC-OFDM UWB system.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A novel joint estimation and compensation algorithm for non-idealities of analog front-end in DC-OFDM system.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials.
ACM Trans. Design Autom. Electr. Syst., 2012

Comments on "Estimation of Carrier Frequency Offset With I/Q Mismatch Using Pseudo-Offset Injection in OFDM Systems".
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 2.4GHz to 3.86GHz digitally controlled oscillator with 18.5kHz frequency resolution using single PMOS varactor.
IEICE Electron. Express, 2012

Carrier Frequency Offset estimation in the Presence of I/Q Mismatch for Wideband OFDM systems.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A 1.2 V 1.0-GS/s 8-bit Voltage-Buffer-Free Folding and interpolating ADC.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A cancellation technique for output-dependent delay differences in high-accuracy DACs.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A digitally calibrated current-steering DAC with current-splitting array.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A time-to-digital converter based AFC for wideband frequency synthesizer.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Output-dependent delay cancellation technique for high-accuracy current-steering DACs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

A low power programmable band-pass filter with novel pseudo-resistor for portable biopotential acquisition system.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
A Parallel Early-Pruned K-Best MIMO Signal Detector Up to 1.9Gb/s.
Wirel. Pers. Commun., 2011

Reconfigurable baseband processing architecture for communication.
IET Comput. Digit. Tech., 2011

A 22-mW 2.2%-EVM UWB Transmitter Using On-Chip Transformer and LO Leakage Calibration.
IEICE Trans. Electron., 2011

A 5.5mW 80-400MHz Gm-C low pass filter with a unique auto-tuning system.
IEICE Electron. Express, 2011

A 6.2-9.5 GHz receiver for Wimedia MB-OFDM and China UWB standard.
Sci. China Inf. Sci., 2011

A current-mode RF transmitter for 6-9 GHz MB-OFDM UWB application.
Sci. China Inf. Sci., 2011

A dual-mode VCO based low-power synthesizer with optimized automatic frequency calibration for software-defined radio.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A harmonic-suppressed regenerative divide-by-5 frequency divider for UWB applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Nyquist-rate time-interleaved current-steering DAC with dynamic channel matching.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 80-400 MHz 74 dB-DR Gm-C low-pass filter with a unique auto-tuning system.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Class-AB CMOS buffer with floating class-AB control.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Area efficient LDPC decoder design for parallel layered decoding.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A 1.2 V 70 mA low drop-out voltage regulator in 0.13 µm CMOS process.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A 12-bit 50-MSPS SHA-less opamp-sharing Analog-to-Digital converter in 65nm CMOS.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Low phase noise injection-locked doubler-based quadrature CMOS VCO.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A low-voltage differential injection locked divider with forward body bias.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- muhboxm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Joint estimation and compensation for front-end imperfection in MB-OFDM UWB systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 0.22 pJ/step subsampling ADC with fast input-tracking sampling and simplified opamp sharing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A fractional-N frequency synthesizer for cellular and short range multi-standard wireless receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A current-mode 6-9GHz UWB transmitter with output power flattening technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A sideband-suppressed low-power synthesizer for 14-band dual-carrier MB-OFDM UWB transceivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

QuickYield: an efficient global-search based parametric yield estimation with performance constraints.
Proceedings of the 47th Design Automation Conference, 2010

2009
A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A Low Power Low Voltage 16 Bit Audio SigmaDelta Modulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Novel Operational Amplifier for Low-voltage Low-power SC Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
Design of Highly-Parallel, 2.2Gbps Throughput Signal Detector for MIMO Systems.
Proceedings of IEEE International Conference on Communications, 2008

2007
A Novel Synchronizer for OFDM-based UWB System on New Preamble Design.
Proceedings of the IEEE 18th International Symposium on Personal, 2007

A Power-Optimized CMOS Quadrature VCO with Wide-Tuning Range for UWB Receivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication System.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A High-Speed High-Resolution Low-Distortion CMOS Bootstrapped Switch.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An implementation of a CMOS down-conversion mixer for GSM1900 receiver.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2003
Periodic steady-state analysis of coupled ODE-AE-CGE systems for MOS RF autonomous circuit simulation.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Iterative solution of ODE-PDE-AE systems for RF circuit simulation.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002


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