Junnosuke Suzuki
Orcid: 0009-0002-5273-8448
According to our database1,
Junnosuke Suzuki
authored at least 8 papers
between 2020 and 2024.
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Bibliography
2024
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision.
IEEE Access, 2024
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2023
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
2022
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation.
Int. J. Netw. Comput., 2021
2020
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation.
Proceedings of the Eighth International Symposium on Computing and Networking, 2020