Junki Park

Orcid: 0000-0001-5662-657X

According to our database1, Junki Park authored at least 9 papers between 2016 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
NN-LUT: neural approximation of non-linear operations for efficient transformer inference.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2020
GeCo: Classification Restricted Boltzmann Machine Hardware for On-Chip Semisupervised Learning and Bayesian Inference.
IEEE Trans. Neural Networks Learn. Syst., 2020

Balancing Computation Loads and Optimizing Input Vector Loading in LSTM Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

OPTIMUS: OPTImized matrix MUltiplication Structure for Transformer neural network accelerator.
Proceedings of the Third Conference on Machine Learning and Systems, 2020

2019
Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines.
IEICE Electron. Express, 2019

Peregrine: A Flexible Hardware Accelerator for LSTM with Limited Synaptic Connection Patterns.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Maximizing system performance by balancing computation loads in LSTM accelerators.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
GeCo: classification restricted Boltzmann machine hardware for on-chip learning.
Proceedings of the International Symposium on Rapid System Prototyping, 2017

2016
Area-efficient one-cycle correction scheme for timing errors in flip-flop based pipelines.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016


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