Junho Cheon

According to our database, Junho Cheon authored at least 6 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory.

Myoungsub Kim, Yooncheol Bae, Jaehyuk Park, Jeongho Yeon, Hyungjoon Shim, Sehyun Jin, Hyunsoo Kim, Sangchul Oh, Gapsok Do, Dongyeol Yun, Hyung Dong Lee, David Ahn, Junghun Lee, Muhui Park, Junghyuk Yoon, Jeongho Yi, Taekseung Kim, Gain Park, Seoungju Chung, Junho Cheon, Sujin Chae, Namkyun Park, Kyunghoon Kim, Dongyean Oh, Jaeyun Yi, Seonyong Cha

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Improvement of MAC Accuracy using Oxygen Diffusion Barriers in Resistive Synaptic Cell Arrays.

Youngjae Kwon, Won-Tae Koo, Sangsu Park, Dong Ik Suh, Gunhee Lee, Hyung Dong Lee, Youngbae Ahn, Dohee Kim, Seungwook Ryu, Hoseok Em, Seokjoon Kang, Chang Won Jeong, Junho Cheon, Hyejung Choi, Soo Gil Kim, Seho Lee, Jaeyun Yi, Seonyong Cha

Proceedings of the IEEE International Memory Workshop, 2024

2015

A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory.

Dong-Hwan Jin, Ji-Wook Kwon, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Junho Cheon, Seung-Tak Ryu

IEEE J. Solid State Circuits, 2015

Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology.

Junho Cheon, Insoo Lee, Changyong Ahn, Milos Stanisavljevic, Aravinthan Athmanathan, Nikolaos Papandreou, Haris Pozidis, Evangelos Eleftheriou, Min-Chul Shin, Taekseung Kim, Jong-Ho Kang, Jun Hyun Chun

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

Auto-Scaling Overdrive Method Using Adaptive Charge Amplification for PRAM Write Performance Enhancement.

Sukhwan Choi, Hyunsik Kim, Seungchul Jung, Si-Duk Sung, Young-sub Yuk, Hyuck-Sang Yim, Yoonjae Shin, Junho Cheon, Changyong Ahn, Taekseung Kim, Yongki Brave Kim, Gyu-Hyeong Cho

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory.

Aravinthan Athmanathan, Milos Stanisavljevic, Junho Cheon, Seokjoon Kang, Changyong Ahn, Junghyuk Yoon, Min-Chul Shin, Taekseung Kim, Nikolaos Papandreou, Haris Pozidis, Evangelos Eleftheriou

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014