Junhao Shi

Orcid: 0009-0007-5119-7551

According to our database1, Junhao Shi authored at least 17 papers between 1990 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
Semantic consistency knowledge transfer for unsupervised cross domain object detection.
Appl. Intell., November, 2024

TS-ILM: Class Incremental Learning for Online Action Detection.
Proceedings of the 32nd ACM International Conference on Multimedia, MM 2024, Melbourne, VIC, Australia, 28 October 2024, 2024

2023
In Situ Reconfigurable Continuum Robot with Varying Curvature Enabled by Programmable Tensegrity Building Blocks.
Adv. Intell. Syst., July, 2023

2022
A Predictive Model of Spindle Thermal Error Based on DCGAN.
Proceedings of the 8th International Conference on Mechatronics and Robotics Engineering, 2022

2021
A GAN-based data augmentation method for human activity recognition via the caching ability.
Internet Technol. Lett., 2021

2020
Transition Activity Recognition System based on Standard Deviation Trend Analysis.
Sensors, 2020

Sensor-based activity recognition independent of device placement and orientation.
Trans. Emerg. Telecommun. Technol., 2020

2011
A real-time bimanual 3D interaction method based on bare-hand tracking.
Proceedings of the 19th International Conference on Multimedia 2011, Scottsdale, AZ, USA, November 28, 2011

2007
Boolean Techniques in Testing of Digital Circuits (Boolesche Techniken zum Testen von digitale Schaltkreise)
PhD thesis, 2007

2006
Efficiency of Multi-Valued Encoding in SAT-based ATPG.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

2005
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Bridging fault testability of BDD circuits.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Synthesis of fully testable circuits from BDDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

BDD Circuit Optimization for Path Delay Fault Testability.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003
MuTaTe: an efficient design for testability technique for multiplexor based circuits.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

1990
Nonlinear system identification for cascaded block model: an application to electrode polarization impedance.
IEEE Trans. Biomed. Eng., 1990


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