Jungyul Pyo

According to our database, Jungyul Pyo authored at least 4 papers between 2013 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling.

Min-Su Kim, Ah-Reum Kim, Yong-geol Kim, Chunghee Kim, Dong-Yeop Kim, Jong-Woo Kim, Daeseong Lee, Hyun Lee, Jungyul Pyo, Youngmin Shin, Jae Cheol Son

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016

Single-ended D flip-flop with implicit scan mux for high performance mobile AP.

Min-Su Kim, Chunghee Kim, Yong-geol Kim, Ah-Reum Kim, Jikyum Kim, Juhyun Kang, Daeseong Lee, Changjun Choi, Ilsuk Suh, Jungyul Pyo, Youngmin Shin, Jae Cheol Son

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2015

23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor.

Jungyul Pyo, Youngmin Shin, Hoi-Jin Lee, Sung-il Bae, Min-Su Kim, Kwangil Kim, Ken Shin, Yohan Kwon, Heungchul Oh, Jaeyoung Lim, Dong-Wook Lee, Jongho Lee, Inpyo Hong, Kyungkuk Chae, Heon-Hee Lee, Sung-Wook Lee, Seongho Song, Chunghee Kim, Jin-Soo Park, Heesoo Kim, Sunghee Yun, Ukrae Cho, Jae Cheol Son, Sungho Park

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013

A 1.6 GHz quad-core application processor manufactured in 32 nm high-k metal gate process for smart mobile devices.

Se-Hyun Yang, Jungyul Pyo, Youngmin Shin, Jae Cheol Son

IEEE Commun. Mag., 2013