Jungsub Kim

According to our database, Jungsub Kim authored at least 8 papers between 2006 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data.

Chi-Li Yu, Jungsub Kim, Lanping Deng, Srinidhi Kestur, Vijaykrishnan Narayanan, Chaitali Chakrabarti

J. Signal Process. Syst., 2011

2009

Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits.

Rajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jungsub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu

IEEE Trans. Dependable Secur. Comput., 2009

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization.

Jungsub Kim, Lanping Deng, Prasanth Mangalagiri, Kevin M. Irick, Kanwaldeep Sobti, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun

IEEE Trans. Computers, 2009

2008

Efficient image reconstruction using partial 2D Fourier transform.

Lanping Deng, Chi-Li Yu, Chaitali Chakrabarti, Jungsub Kim, Vijaykrishnan Narayanan

Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

2007

Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations.

Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun, Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijaykrishnan Narayanan

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms.

Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun

Proceedings of the FPL 2007, 2007

2006

SEAT-LA: A Soft Error Analysis Tool for Combinational Logic.

R. Rajaraman, Jungsub Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations.

G. Chen, Liping Xue, Jungsub Kim, Kanwaldeep Sobti, Lanping Deng, Xiaobai Sun, Nikos Pitsianis, Chaitali Chakrabarti, Mahmut T. Kandemir, Narayanan Vijaykrishnan

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006