Jung Yun Choi

According to our database, Jung Yun Choi authored at least 13 papers between 2001 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage.

Hye Rim Ji, Jong Seong Kim, Jung Yun Choi, Jee Hyong Lee

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits.

Seyoung Kim, Seungho Yang, Hyein Lim, Hyein Lee, Jongwook Jeon, Jung Yun Choi, Jaeha Kim

IEEE Access, 2023

2021

Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs.

Hyojin Choi, In Huh, Seungju Kim, Jeonghoon Ko, Changwook Jeong, Hyeonsik Son, Kiwon Kwon, Joonwan Chai, Younsik Park, Jaehoon Jeong, Daesin Kim, Jung Yun Choi

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2016

Sequential analysis driven reset optimization to improve power, area and routability.

Srihari Yechangunja, Raj Shekhar, Mohit Kumar, Nikhil Tripathi, Abhishek Mittal, Abhishek Ranjan, Jianfeng Liu, Minyoung Mo, Kyung Tae Do, Jung Yun Choi, SungHo Park

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Adaptive delay monitoring for wide voltage-range operation.

Jongho Kim, Gunhee Lee, Kiyoung Choi, Yonghwan Kim, Wook Kim, Kyung Tae Do, Jung Yun Choi

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Coarse-grained Structural Placement for a Synthesized Parallel Multiplier.

Sungmin Bae, Hyung-Ock Kim, Jung Yun Choi, Jaehong Park

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Clock domain crossing aware sequential clock gating.

Jianfeng Liu, Mi-Suk Hong, Kyung Tae Do, Jung Yun Choi, Jaehong Park, Mohit Kumar, Manish Kumar, Nikhil Tripathi, Abhishek Ranjan

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2013

Early-life-failure detection using SAT-based ATPG.

Matthias Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra, Bernd Becker

Proceedings of the 2013 IEEE International Test Conference, 2013

Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics.

Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Matthias Sauer, Bernd Becker, Subhasish Mitra

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2010

Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS.

Hyung-Ock Kim, Bong Hyun Lee, Jong-Tae Kim, Jung Yun Choi, Kyu-Myung Choi, Youngsoo Shin

IEEE Trans. Very Large Scale Integr. Syst., 2010

2007

Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.

Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi

IEEE Trans. Very Large Scale Integr. Syst., 2007

Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.

Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2001

Backward Propagated Capacitance Model for Register Transfer Level Power Estimation.

Jung Yun Choi, Young Hwan Kim, Kyoung-Rok Cho

VLSI Design, 2001