Jung-Woo Sull
Orcid: 0000-0002-4063-998X
According to our database1,
Jung-Woo Sull
authored at least 7 papers
between 2020 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
2020
2021
2022
2023
2024
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024
2023
An 8-GHz Octa-Phase Clock Corrector with Phase and Duty-Cycle Correction in 40-nm CMOS.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
2022
An 8-GHz Octa-Phase Error Corrector With Coprime Phase Comparison Scheme in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
Proceedings of the International SoC Design Conference, 2020