Jung-Pil Lim

According to our database, Jung-Pil Lim authored at least 2 papers between 2020 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/ps Slew Rate for 8K Displays and Beyond.

Kyungho Ryu, Ji-Yong Jeong, Jung-Pil Lim, Kil-Hoon Lee, Kyongho Kim, Yongil Kwon, Seongjong Yoo, Siwoo Kim, Hyun-Wook Lim, Jae-Youl Lee

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2020

An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits.

Kyungho Ryu, Kil-Hoon Lee, Jung-Pil Lim, Jinho Kim, Han Su Pae, Junho Park, Hyun-Wook Lim, Jae-Youl Lee

IEEE Trans. Very Large Scale Integr. Syst., 2020