Juncheng Chen
Orcid: 0000-0001-8047-0691
According to our database1,
Juncheng Chen
authored at least 25 papers
between 2016 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Securing Against Side-Channel Attacks With Wide-Range In Situ Random Voltage Dithering on Async-Logic AES Engine.
IEEE Trans. Very Large Scale Integr. Syst., October, 2024
A Novel Feature Fusion Approach for Classification of Motor Imagery EEG Based on Hierarchical Extreme Learning Machine.
Cogn. Comput., March, 2024
A Novel Non-profiling Side-Channel Attack on Masked Devices with Connectivity Matrix.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
A Residual-Remainder Coupled Unlimited Sampling Framework for High Dynamic Range Signal Conversion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Validation of MODIS LAI Product Using Upscaling Sentinel-2 Decameter-Scale LAI and Field Measured LAI.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2023
Proceedings of the 9th International Conference on Computing and Artificial Intelligence, 2023
Proceedings of the 2023 7th International Conference on Computer Science and Artificial Intelligence, 2023
2022
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2022
An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022
2021
A Novel Normalized Variance-Based Differential Power Analysis Against Masking Countermeasures.
IEEE Trans. Inf. Forensics Secur., 2021
Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Classification of epilepsy period based on combination feature extraction methods and spiking swarm intelligent optimization algorithm.
Concurr. Comput. Pract. Exp., 2021
The Improved ELM Algorithms Optimized by Bionic WOA for EEG Classification of Brain Computer Interface.
IEEE Access, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2018
IEEE Trans. Intell. Transp. Syst., 2018
基于关联规则的交通事故影响因素的挖掘 (Influence Factors Mining of Traffic Accidents Based on Association Rules).
计算机科学, 2018
2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Proceedings of the Social Computing, 2016
Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016
Classification Based on Multilayer Extreme Learning Machine for Motor Imagery Task from EEG Signals.
Proceedings of the 7th Annual International Conference on Biologically Inspired Cognitive Architectures, 2016