Jun Yin
Orcid: 0000-0002-4195-4551Affiliations:
- University of Macau, State Key Laboratory of Analog and Mixed-Signal VLSI, China
- Hong Kong University of Science and Technology, Department of Electronic and Computer Engineering, Hong Kong (PhD 2013)
According to our database1,
Jun Yin
authored at least 69 papers
between 2010 and 2024.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2024
A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment.
IEEE J. Solid State Circuits, December, 2024
IEEE J. Solid State Circuits, November, 2024
A Complementary Drain-Grounded VCO-PA Improving Transmit Efficiency Over a Wide EIRP Range.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2024
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024
A 12.9-to-24 GHz Dual-Mode Multi-Coil VCO Achieving 199.2 dBc/Hz Peak FoM<sub>T</sub> in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024
A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
A 5.6-dB Noise Figure, 63-86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
19.4 A 0.07 mm<sup>2</sup> 20-to-23.8GHz 8-phase Oscillator Incorporating Magnetic + Dual-Injection Coupling Achieving 189.2dBc/Hz FoM@10 MHz and 200.7dBc/Hz FoMA in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A 0.0043-mm<sup>2</sup> 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023
A 3.57-mW 2.88-GHz Multi-Phase Injection-Locked Ring-VCO With a 200-kHz 1/f³ Phase Noise Corner.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
IEEE Trans. Circuits Syst. II Express Briefs, 2023
A 22.4-to-26.8GHz Dual-Path-Synchronized Quad-Core Oscillator Achieving -138dBc/Hz PN and 193.3dBc/Hz FoM at 10MHz Offset from 25.8GHz.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A ULP Long-Range Active-RF Tag with Automatic Antenna-Interface Calibration Achieving 20.5% TX Efficiency at -22dBm EIRP, and -60.4dBm Sensitivity at 17.8nW RX Power.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 13.5-to-28.8GHz 72.3%-Locking Range Multi-Phase Injection-Locked Frequency Tripler with Improved Output Power and Wideband Subharmonic-Spur Rejection in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 6-to-7.5-GHz 54-fs<sub>rms</sub> Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2021
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
An 800 MHz-to-3.3 GHz 20-MHz Channel Bandwidth WPD CMOS Power Amplifier For Multiband Uplink Radio Transceivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Wide-PCE-Dynamic-Range CMOS Cross-Coupled Differential-Drive Rectifier for Ambient RF Energy Harvesting.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Int. J. Circuit Theory Appl., 2021
A Periodically Time-Varying Inductor Applied to The Class-D VCO for Phase Noise Improvement.
Proceedings of the 47th ESSCIRC 2021, 2021
A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2<sup>nd</sup>-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 1-V 4-mW Differential-Folded Mixer With Common-Gate Transconductor Using Multiple Feedback Achieving 18.4-dB Conversion Gain, +12.5-dBm IIP3, and 8.5-dB NF.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer With Integrated Transformer-Based Gate Inductor and IM2 Injection Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools.
IEEE Trans. Circuits Syst., 2020
A Single-Pin Antenna Interface RF Front End Using a Single-MOS DCO-PA and a Push-Pull LNA.
IEEE J. Solid State Circuits, 2020
A Multiband FDD SAW-Less Transmitter for 5G-NR Featuring a BW-Extended N-Path Filter-Modulator, a Switched-BB Input, and a Wideband TIA-Based PA Driver.
IEEE J. Solid State Circuits, 2020
10.1 A 1.4-to-2.7GHz FDD SAW-Less Transmitter for 5G-NR Using a BW-Extended N-Path Filter-Modulator, an Isolated-BB Input and a Wideband TIA-Based PA Driver Achieving <-157.5dBc/Hz OB Noise.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
17.9 A 9mW 54.9-to-63.5GHz Current-Reuse LO Generator with a 186.7dBc/Hz FoM by Unifying a 20GHz 3<sup>rd</sup>-Harmonic-Rich Current-Output VCO, a Harmonic-Current Filter and a 60GHz TIA.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A 0.12-mm<sup>2</sup> 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 5.1-to-7.3 mW, 2.4-to-5 GHz Class-C Mode-Switching Single-Ended-Complementary VCO Achieving >190 dBc/Hz FoM.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
CMOS Cross-Coupled Differential-Drive Rectifier in Subthreshold Operation for Ambient RF Energy Harvesting - Model and Analysis.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019
A 0.0056-mm<sup>2</sup> -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs.
IEEE J. Solid State Circuits, 2019
A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA.
Integr., 2019
Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm.
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
A 0.032-mm<sup>2</sup> 0.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A Coin-Battery-Powered LDO-Free 2.4-GHz Bluetooth Low-Energy Transmitter With 34.7% Peak System Efficiency.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 0.18-V 382-µW Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS.
IEEE J. Solid State Circuits, 2018
Low-Phase-Noise Wideband Mode-Switching Quad-Core-Coupled mm-wave VCO Using a Single-Center-Tapped Switched Inductor.
IEEE J. Solid State Circuits, 2018
An Inverse-Class-F CMOS Oscillator With Intrinsic-High-Q First Harmonic and Second Harmonic Resonances.
IEEE J. Solid State Circuits, 2018
Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications.
Proceedings of the 15th International Conference on Synthesis, 2018
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.0056mm<sup>2</sup> all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
An inverse-class-F CMOS VCO with intrinsic-high-Q 1<sup>st</sup>- and 2<sup>nd</sup>-harmonic resonances for 1/f<sup>2</sup>-to-1/f<sup>3</sup> phase-noise suppression achieving 196.2dBc/Hz FOM.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6% (14.5%) System Efficiency at 6-dBm (0-dBm) P<sub>out</sub>.
IEEE J. Solid State Circuits, 2017
24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz Frequency Synthesizer for Software-Defined Radios in 0.13-µm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A Time-Interleaved Ring-VCO with Reduced 1/f<sup>3</sup> Phase Noise Corner, Extended Tuning Range and Inherent Divided Output.
IEEE J. Solid State Circuits, 2016
2.7 A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
A high-Q spiral inductor with dual-layer patterned floating shield in a class-B VCO achieving a 190.5-dBc/Hz FoM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2014
A 21-48 GHz Subharmonic Injection-Locked Fractional-N Frequency Synthesizer for Multiband Point-to-Point Backhaul Communications.
IEEE J. Solid State Circuits, 2014
Proceedings of the Symposium on VLSI Circuits, 2014
2013
IEEE J. Solid State Circuits, 2013
A CMOS 21-48GHz fractional-N synthesizer employing ultra-wideband injection-locked frequency multipliers.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2010
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010