Jun Yao
Affiliations:- Huawei Technologies Co. Ltd., Beijing, China
- Nara Institute of Science and Technology, Graduate School of Information Science, Ikoma, Japan (former)
- Kyoto University, Graduate School of Informatics, Japan (former)
According to our database1,
Jun Yao
authored at least 24 papers
between 2003 and 2015.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2015
Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators.
IEICE Trans. Inf. Syst., 2015
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Lowering the complexity of k-means clustering by BFS-dijkstra method for graph computing.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015
2014
IEEE Micro, 2014
A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction.
IEICE Trans. Inf. Syst., 2014
Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults.
IEICE Trans. Inf. Syst., 2014
A globally asynchronous locally synchronous DMR architecture for aggressive low-power fault toleration.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014
A flexibly fault-tolerant FU array processor and its self-tuning scheme to locate permanently defective unit.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014
2013
IEICE Trans. Inf. Syst., 2013
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013
2012
RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
2011
A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth.
J. Comput. Sci. Technol., 2011
IEICE Trans. Inf. Syst., 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
An efficient and reliable 1.5-way processor by fusion of space and time redundancies.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011
2010
A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010
Proceedings of the International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, 2010
2009
Inf. Media Technol., 2009
2008
A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases.
IEICE Trans. Inf. Syst., 2008
2007
SIGARCH Comput. Archit. News, 2007
Distributed Storage Cluster Design for Remote Mirroring Based on Storage Area Network.
J. Comput. Sci. Technol., 2007
2005
Program Phase Detection Based Dynamic Control Mechanisms for Pipeline Stage Unification Adoption.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005
2003
Proceedings of the Advanced Parallel Programming Technologies, 5th International Workshop, 2003