Jun Seomun

According to our database1, Jun Seomun authored at least 12 papers between 2007 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
Early-life-failure detection using SAT-based ATPG.
Proceedings of the 2013 IEEE International Test Conference, 2013

Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Synthesis of Active-Mode Power-Gating Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Thermal-aware body bias modulation for high performance mobile core.
Proceedings of the International SoC Design Conference, 2012

2011
Design and Optimization of Power-Gated Circuits With Autonomous Data Retention.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs.
ACM Trans. Design Autom. Electr. Syst., 2010

Synthesis and implementation of active mode power gating circuits.
Proceedings of the 47th Design Automation Conference, 2010

Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Frequency and yield optimization using power gates in power-constrained designs.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008
Skewed Flip-Flop and Mixed-V<sub>t</sub> Gates for Minimizing Leakage in Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007
Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits.
Proceedings of the 44th Design Automation Conference, 2007


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