Jun-Hong Chen

According to our database¹, Jun-Hong Chen authored at least 21 papers between 2004 and 2023.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of three.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2023

Establishment of extensive artificial intelligence models for kinase inhibitor prediction: Identification of novel PDGFRB inhibitors.

[BibT_eX]

[DOI]

Comput. Biol. Medicine, April, 2023

2022

Discovering a trans-omics biomarker signature that predisposes high risk diabetic patients to diabetic kidney disease.

[BibT_eX]

[DOI]

npj Digit. Medicine, 2022

2020

Animated Character Style Investigation with Decision Tree Classification.

[BibT_eX]

[DOI]

Symmetry, 2020

2019

A Study of Facial Features of American and Japanese Cartoon Characters.

[BibT_eX]

[DOI]

Kun Liu

Jun-Hong Chen

Kang-Ming Chang

Symmetry, 2019

2017

SheddomeDB: the ectodomain shedding database for membrane-bound shed markers.

[BibT_eX]

[DOI]

Wei-Sheng Tien

Jun-Hong Chen

Kun-Pin Wu

BMC Bioinform., 2017

Freeway Travel Time Prediction by Using the GA-Based Hammerstein Recurrent Neural Network.

[BibT_eX]

[DOI]

Proceedings of the Genetic and Evolutionary Computing, 2017

2010

A High-Performance Unified-Field Reconfigurable Cryptographic Processor.

[BibT_eX]

[DOI]

Jun-Hong Chen

Ming-Der Shieh

Wen-Ching Lin

IEEE Trans. Very Large Scale Integr. Syst., 2010

2009

A New Algorithm for High-Speed Modular Multiplication Design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

An Efficient Multiplier/Divider Design for Elliptic Curve Cryptosystem over GF(2m).

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2009

2008

A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

A new look-up table-based multiplier/squarer design for cryptosystems over GF(2m).

[BibT_eX]

[DOI]

Wen-Ching Lin

Jun-Hong Chen

Ming-Der Shieh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

High-speed modular multiplication design for public-key cryptosystems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Exploration of Low-Cost Configurable S-Box Designs for AES Applications.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Embedded Software and Systems, 2008

2007

A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

High-Speed Design of Montgomery Inverse Algorithm over GF(2m).

[BibT_eX]

[DOI]

Ming-Der Shieh

Jun-Hong Chen

Chien-Ming Wu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Design and implementation of efficient Reed-Solomon decoders for multi-mode applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High-speed CRC design for 10 Gbps applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Asynchronous Design of Modular Multiplication Using Adaptive Radix Computation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

VLSI architectural design tradeoffs for sliding-window log-MAP decoders.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography.

[BibT_eX]

[DOI]

Jun-Hong Chen

Ming-Der Shieh

Chien-Ming Wu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

VLSI architecture exploration for sliding-window Log-MAP decoders.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Jun-Hong Chen

Timeline

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