Jun-Ho Choy
Orcid: 0000-0002-8977-5720
According to our database1,
Jun-Ho Choy
authored at least 13 papers
between 2009 and 2024.
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Bibliography
2024
Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects.
Proceedings of the 2024 International Symposium on Physical Design, 2024
A Unified Physics-Based Stochastic Model for EM-Induced Resistance Degradation in BEoL Interconnect Segments.
Proceedings of the IEEE International Reliability Physics Symposium, 2024
A Novel Method for the Determination of Electromigration-Induced Void Nucleation Stresses.
Proceedings of the IEEE International Reliability Physics Symposium, 2024
2023
Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution.
Proceedings of the 2023 International Symposium on Physical Design, 2023
2022
Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022
2019
Assesment of CPI Stress Impact on IC Reliability and Performance in 2.5D/3D Packages.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
An Accurate Assessment of Chip-Package Interaction is a Key Factor for Designing Resilient 3D IC Systems.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
2016
Electromigration assessment for power grid networks considering temperature and thermal stress effects.
Integr., 2016
2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
2014
Accurate full-chip estimation of power map, current densities and temperature for EM assessment.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
2012
Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance.
J. Electron. Test., 2012
2009
Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009