Jun Hayakawa
According to our database1,
Jun Hayakawa
authored at least 8 papers
between 2007 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
2008
2010
2012
2014
2016
2018
2020
0
1
2
3
4
3
1
1
1
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
Proceedings of the 23rd IEEE International Conference on Intelligent Transportation Systems, 2020
2019
Proceedings of the 2019 IEEE Intelligent Vehicles Symposium, 2019
2010
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme.
IEEE J. Solid State Circuits, 2010
Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit.
IEICE Trans. Electron., 2010
Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits.
IEICE Trans. Electron., 2010
2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read.
IEEE J. Solid State Circuits, 2008
2007
2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007