A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications.

[BibT_eX]

[DOI]

Lizhou Wu

Chenyang Zhao

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023

UArch: A Super-Resolution Processor With Heterogeneous Triple-Core Architecture for Workloads of U-Net Networks.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., June, 2023

A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023

SPARK: An automatic Score-Power-Area efficient RISC-V processor microarchitecture SeeKer.

[BibT_eX]

[DOI]

Qiang Li

Jun Tao

Jun Han

Microelectron. J., February, 2023

A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity.

[BibT_eX]

[DOI]

Microelectron. J., 2023

SVP: Safe and Efficient Speculative Execution Mechanism through Value Prediction.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

Coupled Data Prefetch and Cache Partitioning Scheme for CPU-Accelerator System.

[BibT_eX]

[DOI]

Zengshi Wang

Chao Fu

Jun Han

Proceedings of the 15th IEEE International Conference on ASIC, 2023

General Vector Instruction Extension for GF(2m) Polynomial Operation in Post-quantum Cryptography.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

UACT: A Unified Energy-efficient Computing Architecture for CNN and TCNN.

[BibT_eX]

[DOI]

Yufan Chen

Xuyang Duan

Jun Han

Proceedings of the 15th IEEE International Conference on ASIC, 2023

Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

2022

LosaTM: A Hardware Transactional Memory Integrated With a Low-Overhead Scenario-Awareness Conflict Manager.

[BibT_eX]

[DOI]

Chao Fu

Li Wan

Jun Han

IEEE Trans. Parallel Distributed Syst., 2022

A High-Performance Domain-Specific Processor With Matrix Extension of RISC-V for Module-LWE Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A High-Speed NTT-Based Polynomial Multiplication Accelerator with Vector Extension of RISC-V for Saber Algorithm.

[BibT_eX]

[DOI]

Honglin Kuang

Yifan Zhao

Jun Han

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic Scheduling for Graph Convolutional Networks.

[BibT_eX]

[DOI]

Ruiqi Xie

Jun Yin

Jun Han

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

MC-LSTM: Real-Time 3D Human Action Detection System for Intelligent Healthcare Applications.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2021

A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor.

[BibT_eX]

[DOI]

Microelectron. J., 2021

An energy-efficient crypto-extension design for RISC-V.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC.

[BibT_eX]

[DOI]

Microelectron. J., 2021

A hardware-efficient dual-source data replication and local broadcast mechanism in distributed shared caches.

[BibT_eX]

[DOI]

Chao Fu

Yuchao Zhou

Jun Han

Microelectron. J., 2021

A Heterogeneous Full-stack AI Platform for Performance Monitoring and Hardware-specific Optimizations.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

A Multi-Layer Parallel Hardware Architecture for Homomorphic Computation in Machine Learning.

[BibT_eX]

[DOI]

Guozhu Xin

Yifan Zhao

Jun Han

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A Synthesizable 0.0060mm2 VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

Mini-HOG: An Area-efficient and Low-power HOG Accelerator with SW/HW co-design for Real-time Pedestrian Detection.

[BibT_eX]

[DOI]

Ruiqi Xie

Jun Han

Proceedings of the 14th IEEE International Conference on ASIC, 2021

A CNN Hardware Accelerator Designed for YOLO Algorithm Based on RISC-V SoC.

[BibT_eX]

[DOI]

Xinyu Qin

Xudong Liu

Jun Han

Proceedings of the 14th IEEE International Conference on ASIC, 2021

An Energy-Efficient Image Denoising Accelerator with Depth-wise Separable Convolution and Fused-Layer Architecture.

[BibT_eX]

[DOI]

Xuyang Duan

Ruiqi Xie

Jun Han

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

An Optimization Toolchain Design of Deep Learning Deployment Based on Heterogeneous Computing Platform.

[BibT_eX]

[DOI]

Jun Yin

Jun Han

Xiaodong Zhang

Proceedings of the 2020 International Conference on Wireless Communications and Signal Processing (WCSP), 2020

A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Design Methodology of Clock Polarity Inversion Technique for Frequency Dividers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

A Real-Time and Hardware-Efficient Processor for Skeleton-Based Action Recognition With Lightweight Convolutional Neural Network.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Skeleton-based Action Recognition System for Medical Condition Detection.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Countering power analysis attacks by exploiting characteristics of multicore processors.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2018

MiniTracker: A Lightweight CNN-based System for Visual Object Tracking on Embedded Device.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

2017

A multi-core-based heterogeneous parallel turbo decoder.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

Instruction set extension and hardware acceleration for SVM application toward a vector processor.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2017

FPGA-based efficient implementation of SURF algorithm.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Fp2 arithmetic acceleration based on modified Barrett modular multiplication algorithm.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A high utilization FPGA-based accelerator for variable-scale convolutional neural network.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A configurable nonlinear operation unit for neural network accelerator.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Cryptographie coprocessor design for IoT sensor nodes.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

A low-cost and energy-efficient EEG processor for continuous seizure detection using wavelet transform and AdaBoost.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015

Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

A 65 nm Cryptographic Processor for High Speed Pairing Computation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 1.5-D Multi-Channel EEG Compression Algorithm Based on NLSPIHT.

[BibT_eX]

[DOI]

IEEE Signal Process. Lett., 2015

A configurable SoC design for information security.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A low-cost SoC implementation of AES algorithm for bio-signals.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A SIMD multiplier-accumulator design for pairing cryptography.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Motion artifact removal based on ICA for ambulatory ECG monitoring.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Exploration for energy-efficient ECC decoder of WBAN.

[BibT_eX]

[DOI]

Tianchan Guan

Jun Han

Xiaoyang Zeng

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

A 16-Core Processor With Shared-Memory and Message-Passing Communications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

An error-resilient wavelet-based ECG processor under voltage overscaling.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013

Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

An Ultra-Low Power QRS Complex Detection Algorithm Based on Down-Sampling Wavelet Transform.

[BibT_eX]

[DOI]

IEEE Signal Process. Lett., 2013

Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Robustness Analysis of Mesh-Based Network-on-Chip Architecture under Flooding-Based Denial of Service Attacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Eighth International Conference on Networking, 2013

A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

Low power design for FIR filter.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Highly flexible WBAN transmit-receive system based on USRP.

[BibT_eX]

[DOI]

Tianchan Guan

Jun Han

Xiaoyang Zeng

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Design of a high throughput configurable variable-length FFT processor based on switch network architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

An ultra low-power and area-efficient baseband processor for WBAN transmitter.

[BibT_eX]

[DOI]

Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2013

A hardware-efficient variable-length FFT processor for low-power applications.

[BibT_eX]

[DOI]

Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2013

2012

A High Speed Reconfigurable Face Detection Architecture Based on AdaBoost Cascade Algorithm.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2012

Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2012

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2012

A low power ASIP for precision configurable FFT processing.

[BibT_eX]

[DOI]

Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012

2011

Design of a single-ended cell based 65nm 32×32b 4R2W register file.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A security processor based on MIPS 4KE architecture.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Analysis of adaptive support-weight based stereo matching for hardware realization.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A NoC-based multi-core architecture for IEEE 802.11i CCMP.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A control scheme for a 65nm 32×32b 4-read 2-write register file.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

Optimized digital automatic gain control for DVB-S2 system.

[BibT_eX]

[DOI]

Proceedings of the 2010 Wireless Telecommunications Symposium, 2010

Robust and reliable frame synchronization method for DVB-S2 system.

[BibT_eX]

[DOI]

Proceedings of the 2010 Wireless Telecommunications Symposium, 2010

2009

A multi-task-oriented security processing architecture with powerful extensibility.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Tracking loop for IR-UWB communications in IEEE 802.15 multi-path channels.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Optimal frame synchronization for DVB-S2.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A full-custom design of AES SubByte module with signal independent power consumption.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A low-cost cryptographic processor for security embedded system.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

An Energy-Proportion Synchronization Method for IR-UWB Communications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low-cost and High-performance SoC Design for OMA DRM2 Applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

A high-performance platform-based SoC for information security.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Jun Han

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