Jun Cao

According to our database, Jun Cao authored at least 28 papers between 2000 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology.

Bo Zhang, Anand Vasani, Ashutosh Sinha, Alireza Nilchi, Haitao Tong, Lakshmi P. Rao, Karapet Khanoyan, Hamid Hatamkhani, Xiaochen Yang, Xin Meng, Alexander Wong, Jun Kim, Ping Jing, Yehui Sun, Ali Nazemi, Dean Liu, Anthony Brewster, Jun Cao, Afshin Momtaz

IEEE J. Solid State Circuits, January, 2024

18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS.

Guansheng Li, Adesh Garg, Tim He, Ullas Singh, Jiawen Zhang, Lakshmi P. Rao, Chang Liu, Meisam Honarvar Nazari, Yang Liu, Yong Liu, Heng Zhang, Tamer A. Ali, Hyo-Gyuem Rhew, Jiayoon Ru, Delong Cui, Ali Nazemi, Bo Zhang, Afshin Momtaz, Jun Cao

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology.

Bo Zhang, Anand Vasani, Ashutosh Sinha, Alireza Nilchi, Haitao Tong, Lakshmi P. Rao, Karapet Khanoyan, Hamid Hatamkhani, Xiaochen Yang, Xin Meng, Alexander Wong, Jun Kim, Ping Jing, Yehui Sun, Ali Nazemi, Dean Liu, Anthony Brewster, Jun Cao, Afshin Momtaz

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2017

29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS.

Jun Cao, Delong Cui, Ali Nazemi, Tim He, Guansheng Li, Burak Çatli, Mehdi Khanpour, Kangmin Hu, Tamer A. Ali, Heng Zhang, Hairong Yu, Ben Rhew, Shiwei Sheng, Yonghyun Shim, Bo Zhang, Afshin Momtaz

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS.

Bharath Raghavan, Aida Varzaghani, Lakshmi P. Rao, Henry Park, Xiaochen Yang, Zhi Huang, Yu Chen, Rama Kattamuri, Chunhui Wu, Bo Zhang, Jun Cao, Afshin Momtaz, Namik Kocaman

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS.

Delong Cui, Heng Zhang, Nick Huang, Ali Nazemi, Burak Çatli, Hyo-Gyuem Rhew, Bo Zhang, Afshin Momtaz, Jun Cao

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links.

Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz

IEEE J. Solid State Circuits, 2015

An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS.

Sui Huang, Jun Cao, Michael M. Green

IEEE J. Solid State Circuits, 2015

3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS.

Ali Nazemi, Kangmin Hu, Burak Çatli, Delong Cui, Ullas Singh, Tim He, Zhi Chao Huang, Bo Zhang, Afshin Momtaz, Jun Cao

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Standing wave based clock distribution technique with application to a 10 × 11 Gbps transceiver in 28 nm CMOS.

Guansheng Li, Wooram Lee, Delong Cui, Bo Zhang, Afshin Momtaz, Jun Cao

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS.

Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Chao Huang, Afshin Momtaz, Jun Cao

IEEE J. Solid State Circuits, 2014

A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS.

Adesh Garg, Ullas Singh, Nick Huang, Wayne Wong, Bin Liu, Zhi Chao Huang, Afshin Momtaz, Jun Cao

Proceedings of the Symposium on VLSI Circuits, 2014

2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS.

Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Huang, Afshin Momtaz, Jun Cao

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

8.8 An 8.2-to-10.3Gb/s full-rate linear reference-less CDR without frequency detector in 0.18μm CMOS.

Sui Huang, Jun Cao, Michael M. Green

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS.

Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Deyi Pi, Anand Vasani, Zhi Chao Huang, Burak Çatli, Afshin Momtaz, Jun Cao

IEEE J. Solid State Circuits, 2013

Non-idealities in linear CDR phase detectors.

Jun Cao, Sui Huang, Michael M. Green

Int. J. Circuit Theory Appl., 2013

A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS.

Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS.

Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Dave Pi, Anand Vasani, Zhi Chao Huang, Afshin Momtaz, Jun Cao

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission.

Delong Cui, Bharath Raghavan, Ullas Singh, Anand Vasani, Zhi Chao Huang, Deyi Pi, Mehdi Khanpour, Ali Nazemi, Hassan Maarefi, Wei Zhang, Tamer A. Ali, Nick Huang, Bo Zhang, Afshin Momtaz, Jun Cao

IEEE J. Solid State Circuits, 2012

A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission.

Delong Cui, Bharath Raghavan, Ullas Singh, Anand Vasani, Zhi Chao Huang, Deyi Pi, Mehdi Khanpour, Ali Nazemi, Hassan Maarefi, Tamer A. Ali, Nick Huang, Wei Zhang, Bo Zhang, Afshin Momtaz, Jun Cao

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications.

Namik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui, Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz

IEEE J. Solid State Circuits, 2011

11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applications.

Namik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui, Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber.

Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz

IEEE J. Solid State Circuits, 2010

2009

21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber.

Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007

A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-µm CMOS.

Afshin Momtaz, David Chung, Namik Kocaman, Jun Cao, Mario Caresosa, Bo Zhang, Ichiro Fujimori

IEEE J. Solid State Circuits, 2007

2002

OC-192 transmitter and receiver in standard 0.18-μm CMOS.

Jun Cao, Michael M. Green, Afshin Momtaz, Kambiz Vakilian, David Chung, Keh-Chee Jen, Mario Caresosa, Xin Wang, Wee-Guan Tan, Yijun Cai, Ichiro Fujimori, Armond Hairapetian

IEEE J. Solid State Circuits, 2002

2001

A fully integrated SONET OC-48 transceiver in standard CMOS.

Afshin Momtaz, Jun Cao, Mario Caresosa, Armond Hairapetian, David Chung, Kambiz Vakilian, Michael M. Green, Wee-Guan Tan, Keh-Chee Jen, Ichiro Fujimori, Yijun Cai

IEEE J. Solid State Circuits, 2001

2000

A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8× oversampling ratio.

Ichiro Fujimori, Lorenzo Longo, Armond Hairapetian, Kazushi Seiyama, Steve Kosic, Jun Cao, Shu-Lap Chan

IEEE J. Solid State Circuits, 2000