Julius Edler

According to our database, Julius Edler authored at least 6 papers between 2021 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

An 18-MS/s 76-dB SNDR Continuous-Time Δ Σ Modulator Incorporating an Input Voltage Tracking GmC Loop Filter.

Marcel Runge, Julius Edler, Tobias Kaiser, Kai Misselwitz, Friedel Gerfers

IEEE J. Solid State Circuits, 2023

A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter.

Julius Edler, Marcel Runge, Sebastian Linnhoff, Friedel Gerfers

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 10Bit 6 GS/s Time-Interleaved SAR ADC with a Single Full-Rate Front-End Track-and-Hold.

Sebastian Linnhoff, Frowin Buballa, Julius Edler, Enne Wittenhagen, Urs Hecht, Friedel Gerfers

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

2022

A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS.

Marcel Runge, Julius Edler, Dario Schmock, Tobias Kaiser, Friedel Gerfers

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS.

Julius Edler, Marcel Runge, Friedel Gerfers

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS.

Marcel Runge, Julius Edler, Tobias Kaiser, Friedel Gerfers

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021