Júlio Paisana

According to our database, Júlio Paisana authored at least 4 papers between 2008 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Ultra low power capless LDO with dynamic biasing of derivative feedback.

Jorge O. M. Esteves, João Pereira, Júlio Paisana, Marcelino B. Santos

Microelectron. J., 2013

2008

Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization.

Nuno Dias, Marcelino B. Santos, Floriberto A. Lima, Beatriz Vieira Borges, Júlio Paisana

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification.

João Pedro Oliveira, João Goes, Nuno Paulino, Jorge R. Fernandes, Júlio Paisana

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Adjustable low consumption circuit for monitorization of power source voltages in a SoC.

Rodrigo Duarte, Júlio Paisana, Marcelino B. Santos, Floriberto A. Lima

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008