Julio de Oliveira Filho

Orcid: 0000-0001-5152-4902

Affiliations:
  • TNO, The Hague, The Netherlands


According to our database1, Julio de Oliveira Filho authored at least 22 papers between 2003 and 2024.

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Bibliography

2024
MYRTUS: Multi-layer 360° dYnamic orchestration and interopeRable design environmenT for compute-continUum Systems.
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

2023
Runtime Verification of Learning Properties for Reinforcement Learning Algorithms.
Proceedings of the Proceedings Fifth International Workshop on Formal Methods for Autonomous Systems, 2023

Integral AI-based planning for management of WSNs in military operations.
Proceedings of the 35th IEEE International Conference on Tools with Artificial Intelligence, 2023

2019
A link layer protocol for quantum networks.
Proceedings of the ACM Special Interest Group on Data Communication, 2019

A Bond-Graph Metamodel.
Proceedings of the Formal Aspects of Component Software - 16th International Conference, 2019

CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of reconfigurable systems in unceRtain hybRid envirOnments: Invited paper: CERBERO teams from UniSS, UniCA, IBM Research, TASE, INSA-Rennes, UPM, USI, Abinsula, AmbieSense, TNO, S&T, CRF.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2014
Model-Based Architecture Optimization for Self-Adaptive Networked Signal Processing Systems.
Proceedings of the Eighth IEEE International Conference on Self-Adaptive and Self-Organizing Systems, 2014

2013
Model-based Design of Self-adapting Networked Signal Processing Systems.
Proceedings of the 7th IEEE International Conference on Self-Adaptive and Self-Organizing Systems, 2013

2010
Description and Specialization of Coarse-grained Reconfigurable Architectures.
PhD thesis, 2010

Charge Recycling in Voltage-Dithered Circuits.
J. Low Power Electron., 2010

Evaluation and Design Methods for Processor-Like Reconfigurable Architectures.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009
CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable Arrays.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Low Energy Voltage Dithering in Dual <i>V</i><sub><i>DD</i></sub> Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2008
Self-Localization in a Low Cost Bluetooth Environment.
Proceedings of the Ubiquitous Intelligence and Computing, 5th International Conference, 2008

Evaluating the impact of customized instruction set on coarse grained reconfigurable arrays.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008


2007
CRC - Concepts and Evaluation of Processor-Like Reconfigurable Architectures (CRC - Konzepte und Bewertung prozessorartig rekonfigurierbarer Architekturen).
it Inf. Technol., 2007

Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

2006
Tuning Coarse-Grained Reconfigurable Architectures towards an Application Domain.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2003
A Fast IP-Core Integration Methodology for SoC Design.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Petri Net Based Interface Analysis for Fast IP-Core Integration.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003


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