Julio Costella Vicenzi

Orcid: 0000-0003-3235-9854

According to our database1, Julio Costella Vicenzi authored at least 13 papers between 2018 and 2024.

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Bibliography

2024
TARA: Enhancing Real-Time Network Traffic Classification with Hardware Virtual Layers.
Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

Exploiting Virtual Layers and Pruning for FPGA-Based Adaptive Traffic Classification.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

2023
Multiprovision: a Design Space Exploration tool for multi-tenant resource provisioning in CPU-GPU environments.
Des. Autom. Embed. Syst., December, 2023

Dynamic Offloading for Improved Performance and Energy Efficiency in Heterogeneous IoT-Edge-Cloud Continuum.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Adaptive Inference on Reconfigurable SmartNICs for Traffic Classification.
Proceedings of the Advanced Information Networking and Applications, 2023

2022
Dedicated Shapelet Distance Engine for Time-Series Classification.
IEEE Des. Test, 2022

An energy efficient multi-target binary translator for instruction and data level parallelism exploitation.
Des. Autom. Embed. Syst., 2022

On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

2021
TRIPP: Transparent Resource Provisioning for Multi-Tenant CPU-GPU based Cloud Environments.
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021

2020
Unlocking the Full Potential of Heterogeneous Accelerators by Using a Hybrid Multi-Target Binary Translator.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Hardware Accelerator for Shapelet Distance Computation in Time-Series Classification.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

2019
Boosting SIMD Benefits through a Run-time and Energy Efficient DLP Detection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Runtime Vectorization of Conditional Code and Dynamic Range Loops to ARM NEON Engine.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018


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