Julien Vial

According to our database1, Julien Vial authored at least 4 papers between 2008 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
Is triple modular redundancy suitable for yield improvement?
IET Comput. Digit. Tech., 2009

2008
SoC Yield Improvement: Redundant Architectures to the Rescue?
Proceedings of the 2008 IEEE International Test Conference, 2008

Yield Improvement, Fault-Tolerance to the Rescue?.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Using TMR Architectures for Yield Improvement.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008


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