Julien Ryckaert
Orcid: 0009-0001-0140-3042
According to our database1,
Julien Ryckaert
authored at least 71 papers
between 2005 and 2024.
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Bibliography
2024
IEEE Trans. Very Large Scale Integr. Syst., November, 2024
Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5).
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
On-chip Memory in Accelerator-based Systems: A System Technology Co-Optimization (STCO) Perspective for Emerging Device Technologies.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024
Accelerating Large Language Model Training with In-Package Optical Links for Scale-Out Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Thermal Implications in Scaling High-Performance Server 3D Chiplet-Based 2.5D SoC from FinFET to Nanosheet.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Reliability Physics Symposium, 2024
Thermal Analysis of High-Performance Server SoCs from FinFET to Nanosheet Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs).
Proceedings of the IEEE International Reliability Physics Symposium, 2023
MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
2022
Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
2020
IEEE Comput. Archit. Lett., 2020
Proceedings of the VLSI-SoC: Design Trends, 2020
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2020
2019
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2017
Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
2016
Proceedings of the 2016 on International Symposium on Physical Design, 2016
2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.
Proceedings of the 44th European Solid State Device Research Conference, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Low-power, low-penalty, flip-chip integrated, 10Gb/s ring-based 1V CMOS photonics transmitter.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter.
IEEE J. Solid State Circuits, 2012
Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
A 0.5 mm <sup>2</sup> Power-Scalable 0.5-3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler.
IEEE J. Solid State Circuits, 2010
IEEE J. Solid State Circuits, 2010
A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
Proceedings of IEEE International Conference on Communications, 2008
A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS.
Proceedings of the ESSCIRC 2008, 2008
2007
IEEE J. Solid State Circuits, 2007
A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a.
IEEE J. Solid State Circuits, 2007
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
IEEE J. Sel. Areas Commun., 2006
EURASIP J. Wirel. Commun. Netw., 2006
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Proceedings of IEEE International Conference on Communications, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005