Julien Lamoureux

According to our database1, Julien Lamoureux authored at least 15 papers between 2001 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2010
Fine-grained vs. coarse-grained shift-and-add arithmetic in FPGAs (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009
Accelerating a Virtual Ecology Model with FPGAs.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering.
IEEE Trans. Very Large Scale Integr. Syst., 2008

On the trade-off between power and flexibility of FPGA clock networks.
ACM Trans. Reconfigurable Technol. Syst., 2008

The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units.
Int. J. Reconfigurable Comput., 2008

An Overview of Low-Power Techniques for Field-Programmable Gate Arrays.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007
Clock-Aware Placement for FPGAs.
Proceedings of the FPL 2007, 2007

GlitchLess: an active glitch minimization technique for FPGAs.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

2006
Architecture and CAD for FPGA Clock Networks.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Activity Estimation for Field-Programmable Gate Arrays.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA clock network architecture: flexibility vs. area and power.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005
On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays.
J. Low Power Electron., 2005

2004
An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
On the Interaction Between Power-Aware FPGA CAD Algorithms.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2001
Fast and low-power inner product processor.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001


  Loading...