Julian Viejo
Orcid: 0000-0001-7543-5082Affiliations:
- University of Seville, Spain
According to our database1,
Julian Viejo
authored at least 20 papers
between 2005 and 2023.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2023
2021
An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation.
IEEE Access, 2021
2020
EURASIP J. Adv. Signal Process., 2020
2017
Microelectron. J., 2017
2016
2012
Microprocess. Microsystems, 2012
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012
2011
Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation.
IEEE Trans. Instrum. Meas., 2011
Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells.
J. Low Power Electron., 2011
2010
Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies.
J. Low Power Electron., 2010
Proceedings of the IEEE Fifth International Symposium on Industrial Embedded Systems, 2010
2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
2007
J. Low Power Electron., 2007
Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
2006
J. Low Power Electron., 2006
Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006
2005
Proceedings of the Integrated Circuit and System Design, 2005
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates.
Proceedings of the Integrated Circuit and System Design, 2005