Julian Pavon
Orcid: 0000-0002-8291-509X
According to our database1,
Julian Pavon
authored at least 8 papers
between 2019 and 2024.
Collaborative distances:
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Bibliography
2024
QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
2023
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications.
ACM Trans. Archit. Code Optim., June, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023
2022
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
2021
VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
2020
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020
2019
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019