Julian P. Murphy

According to our database1, Julian P. Murphy authored at least 19 papers between 2004 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2014
A unique and robust single slice FPGA identification generator.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
New abstractions in applied pi-calculus and automated verification of protected executions.
IACR Cryptol. ePrint Arch., 2013

Power Balanced Circuits for Leakage-Power-Attacks Resilient Design.
IACR Cryptol. ePrint Arch., 2013

Safe enclosures: towards cryptographic techniques for server protection.
IACR Cryptol. ePrint Arch., 2013

Voltage Sensing Using an Asynchronous Charge-to-Digital Converter for Energy-Autonomous Environments.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

2012
Mixed Radix Reed-Muller Expansions.
IEEE Trans. Computers, 2012

Asynchronous Physical Unclonable Functions - AsyncPUF.
IACR Cryptol. ePrint Arch., 2012

Clockless Physical Unclonable Functions.
Proceedings of the Trust and Trustworthy Computing - 5th International Conference, 2012

Self-Timed Physically Unclonable Functions.
Proceedings of the 5th International Conference on New Technologies, 2012

2010
Secure Design Flow for Asynchronous Multi-valued Logic Circuits.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

2009
Efficient advanced encryption standard implementation using lookup and normal basis.
IET Comput. Digit. Tech., 2009

Quaternary Reed-Muller Expansions of Mixed Radix Arguments in Cryptographic Circuits.
Proceedings of the ISMVL 2009, 2009

2008
Standard cell and full custom power-balanced logic : ASIC implementation.
PhD thesis, 2008

Conversion driven design of binary to mixed radix circuits.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
Dynamic global security-aware synthesis using SystemC.
IET Comput. Digit. Tech., 2007

2005
Design and Analysis of Dual-Rail Circuits for Security Applications.
IEEE Trans. Computers, 2005

Power-Balanced Self Checking Circuits for Cryptographic Chips.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Power-balanced asynchronous logic.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
Improving the Security of Dual-Rail Circuits.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2004


  Loading...